公开(公告)号：EP3376350A1

公开(公告)日：2018-09-19

申请号：EP18161637.6

申请日：2018-03-14

申请人： Samsung Display Co., Ltd.

发明人： Kim, Kiwook ,  Park, Kyontae ,  Kwon, Hyesong ,  Lee, Dae-won ,  Jeong, Donghoon ,  Kwak, Won-kyu ,  Kim, Kwangmin ,  Moon, Joongsoo ,  Jin, Changkyu ,  Cho, Kyu-sik ,  Cho, Sungho

IPC分类号： G06F3/041 ,  H01L51/00

CPC分类号： H01L27/3276 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04111 ,  H01L24/04 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L27/3223 ,  H01L27/323 ,  H01L51/0097 ,  H01L51/5253 ,  H01L2224/02145 ,  H01L2224/0221 ,  H01L2224/04026 ,  H01L2224/16148 ,  H01L2224/29198 ,  H01L2224/32148 ,  H01L2224/73204 ,  H01L2924/1426

摘要： A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group.

公开(公告)号：EP3176819A3

公开(公告)日：2017-06-28

申请号：EP16199908.1

申请日：2016-11-22

申请人： MediaTek Inc.

发明人： JI, Yan-Liang ,  HSIUNG, Ming-Jen

IPC分类号： H01L23/31

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

摘要翻译： 晶圆级芯片级封装（WLCSP）包括半导体结构和在半导体结构的一部分上形成的第一键合焊盘。 WLCSP进一步包括形成在半导体结构和第一键合焊盘之上的钝化层，暴露第一键合焊盘的部分。 WLCSP进一步包括形成在钝化层上方的导电再分布层以及暴露于钝化层的第一键合焊盘的部分。 WLCSP进一步包括形成在钝化层和导电再分布层之上的平坦化层，暴露导电再分布层的一部分。 WLCSP还包括在平坦化层上形成的凸块下冶金（UBM）层和在UBM层上形成的导电凸块。

公开(公告)号：EP3151272A1

公开(公告)日：2017-04-05

申请号：EP16189368.0

申请日：2016-09-18

申请人： Renesas Electronics Corporation

发明人： TONEGAWA, Takashi

IPC分类号： H01L23/485 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/31 ,  H01L21/31056 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/44 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L29/7802 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/031 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03522 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2924/05042 ,  H01L2924/0509 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/059 ,  H01L2924/0103 ,  H01L2924/00

摘要： Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film (PRO1) provided over an interconnection (M1) and having an opening (OA1), and a plating film (OPM1) provided in the opening (OA1). A slit (SL) is provided in a side face of the opening (OA1), and the plating film (OPM1) is also disposed in the slit (SL). Thus, the slit is provided in the side face of the opening (OA1), and the plating film (OPM1) is also grown in the slit (SL). This results in a long penetration path of a plating solution during subsequent formation of the plating film (OPM1). Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit (SL) is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (M1) pad region).

摘要翻译： 半导体器件的性能得到改善。 半导体器件被配置为具有设置在互连（M1）上方且具有开口（OA1）的保护膜（PRO1）以及设置在开口（OA1）中的镀膜（OPM1）。 狭缝（SL）设置在开口（OA1）的侧面中，并且电镀膜（OPM1）也设置在狭缝（SL）中。 因此，在开口部（OA1）的侧面设置狭缝，在狭缝（SL）中也生长镀膜（OPM1）。 这导致在随后形成电镀膜（OPM1）期间电镀溶液的穿透路径较长。 因此，在互连（焊盘区域）中不太可能形成腐蚀部分。 即使形成腐蚀部分，在互连（焊盘区域）之前牺牲部分狭缝（SL）也被腐蚀，使得可以抑制腐蚀部分扩展到互连（M1）焊盘区域）。

公开(公告)号：EP3176819A2

公开(公告)日：2017-06-07

申请号：EP16199908.1

申请日：2016-11-22

申请人： MediaTek Inc.

发明人： JI, Yan-Liang ,  HSIUNG, Ming-Jen

IPC分类号： H01L23/31

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

摘要翻译： 晶片级芯片级封装（WLCSP）包括半导体结构和形成在半导体结构的一部分上的第一焊盘。 WLCSP还包括形成在半导体结构上的钝化层和第一焊盘，暴露第一焊盘的部分。 WLCSP还包括形成在钝化层上的导电再分布层和由钝化层暴露的第一焊盘的部分。 WLCSP还包括形成在钝化层和导电再分配层上的平坦化层，暴露导电再分布层的一部分。 WLCSP还包括在平坦化层上形成的凸点下 - 冶金（UBM）层和形成在UBM层上的导电凸块。

公开(公告)号：EP1091399A4

公开(公告)日：2002-01-16

申请号：EP98924592

申请日：1998-06-12

申请人： HITACHI LTD

发明人： NAGAI AKIRA ,  UENO TAKUMI ,  AKAHOSHI HARUO ,  EGUSHI SYUJI ,  OGINO MASAHIKO ,  SATO TOSHIYA ,  NISHIMURA ASAO ,  ANJO ICHIRO

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14153 ,  H01L2224/16227 ,  H01L2224/73203 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device is disclosed along with a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads as formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for external connection as electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relax layer being adhered thereto, wherein more than one third of the stress relax layer from a surface thereof is cut away for removal and wherein the stress relax layer is subdivided into a plurality of regions. In accordance with the present invention, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

公开(公告)号：EP1091399A1

公开(公告)日：2001-04-11

申请号：EP98924592.3

申请日：1998-06-12

申请人： Hitachi, Ltd.

发明人： NAGAI, Akira Hitachi Res. Lab. of Hitachi Ltd. ,  UENO, Takumi Hitachi Res. Lab. of Hitachi Ltd. ,  AKAHOSHI, Haruo Hitachi Res. Lab. of Hitachi Ltd. ,  EGUSHI, Syuji Hitachi Res. Lab. of Hitachi Ltd. ,  OGINO, Masahiko Hitachi Res. Lab. of Hitachi Ltd. ,  SATO, Toshiya Hitachi Res. Lab. of Hitachi Ltd. ,  NISHIMURA, Asao Semiconductor & Integrated Cir. ,  ANJO, Ichiro Semiconductor & Integrated Circ.

IPC分类号： H01L21/60 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14153 ,  H01L2224/16227 ,  H01L2224/73203 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device is disclosed along with a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads as formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for external connection as electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relax layer being adhered thereto, wherein more than one third of the stress relax layer from a surface thereof is cut away for removal and wherein the stress relax layer is subdivided into a plurality of regions. In accordance with the present invention, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

摘要翻译： 公开了一种半导体器件及其制造方法，该器件包括布置成形成集成电路的半导体元件，形成在半导体元件的集成电路形成表面侧的多个电极焊盘，用于外部连接的凸起电极 通过导电层电连接到电极焊盘，并且一方面在集成电路形成表面和电极焊盘之间形成的应力松弛层和另一方面的凸块电极和导电层，应力松弛层粘附到其上， 其中来自其表面的应力松弛层的三分之一以上被切除以便去除，并且其中应力松弛层被细分为多个区域。 根据本发明，可以提供能够提供高密度安装方案的半导体器件，同时降低生产成本，提高可靠性。