公开(公告)号：EP2597677B1

公开(公告)日：2014-08-06

申请号：EP11190389.4

申请日：2011-11-23

申请人： ams AG

发明人： Cassidy, Cathal ,  Schrems, Martin ,  Schrank, Franz

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme.

公开(公告)号：EP2854167B1

公开(公告)日：2016-01-20

申请号：EP14176547.9

申请日：2011-11-23

申请人： ams AG

发明人： Cassidy, Cathal ,  Schrems, Martin ,  Schrank, Franz

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/552

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme.

摘要翻译： 该半导体器件包括具有位于的前侧（20），一个基片的金属化（111），其具有上部端子层（22）的半导体基板（10）。 金属化形成通孔从上部终端层，以相对位于前侧处的基板的后侧（21）的后部终端层（13）的基板（23）。 经由包括贯通基板哪个可填充有空气或其它气体的空隙（101）。 焊球（100）关闭的空隙而不完全填充呼叫它。 各种互连的三维集成是通过该方案提供的。

公开(公告)号：EP3176819A3

公开(公告)日：2017-06-28

申请号：EP16199908.1

申请日：2016-11-22

申请人： MediaTek Inc.

发明人： JI, Yan-Liang ,  HSIUNG, Ming-Jen

IPC分类号： H01L23/31

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

摘要： A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

摘要翻译： 晶圆级芯片级封装（WLCSP）包括半导体结构和在半导体结构的一部分上形成的第一键合焊盘。 WLCSP进一步包括形成在半导体结构和第一键合焊盘之上的钝化层，暴露第一键合焊盘的部分。 WLCSP进一步包括形成在钝化层上方的导电再分布层以及暴露于钝化层的第一键合焊盘的部分。 WLCSP进一步包括形成在钝化层和导电再分布层之上的平坦化层，暴露导电再分布层的一部分。 WLCSP还包括在平坦化层上形成的凸块下冶金（UBM）层和在UBM层上形成的导电凸块。

公开(公告)号：EP2865006A4

公开(公告)日：2016-03-23

申请号：EP13808814

申请日：2013-06-25

申请人： ADVANCED MICRO DEVICES INC

发明人： SU MICHAEL ZHUOYING ,  LEI FU ,  KUECHENMEISTER FRANK

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L23/3192 ,  H01L21/76804 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06141 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2224/03 ,  H01L2224/11

摘要： Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the center of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

公开(公告)号：EP2908337A1

公开(公告)日：2015-08-19

申请号：EP14154852.9

申请日：2014-02-12

申请人： ams AG

发明人： Schrems, Martin ,  Stering, Bernhard ,  Etschmaier, Harald

IPC分类号： H01L23/485 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/485 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a cover layer (2) arranged above the TSV at the main surface, a bump contact (6) arranged on the TSV at the further main surface, and a stress relief feature at the main surface or at the further main surface. The stress relief feature is provided to expose the TSV at least partially to the environment, which can be the ambient air, for instance, or any region of the device lying outside the region occupied by the TSV. The stress relief feature can be a channel (8) in an under-bump metallization (5).

摘要翻译： 该半导体器件包括主表面相对的半导体基片（1）与主表面（10）和另一主表面（11），一个TSV（3）贯穿从主表面的基片的另一主表面上，一个盖 层（2）上面的TSV布置在主表面上，在另外主表面上布置所述TSV的凸块（6）接触，并且在所述主表面或在另外主表面上的应力释放特征。 设置在应力消除功能来至少部分地暴露TSV到环境中，其可以是环境空气，例如，或躺由TSV所占据的区域之外的装置的任何区域。 应力消除功能可以在凸块下金属化是一个信道（8）（5）。

公开(公告)号：EP1160856A3

公开(公告)日：2003-02-12

申请号：EP01113016.8

申请日：2001-05-28

申请人： NEC CORPORATION

发明人： Miyazaki, Takashi, c/o NEC Corporation

IPC分类号： H01L23/31 ,  H01L21/68

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75743 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/11

摘要： A flip chip type semiconductor device is provided with a semiconductor chip (10) with a plurality of pad electrodes on one surface. A solder electrode (9) is connected to each pad electrode, and a metallic post (16b) is connected to each solder electrode (9). The surface of the semiconductor chip (10) on a side on which the pad electrodes are provided is coated with an insulating resin layer (11) and whole the pad electrode and solder electrode (9) and part of the metallic post (16b) are buried in the insulating resin layer (11). The remaining portion of the metallic post (16b) is projected from the insulating resin layer (11) to form a protrusion. Then, an outer solder electrode (13) is formed so as to cover this protrusion (16b). The outer solder electrodes (13) are arranged in a matrix on the insulating resin layer (11). The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode (13) and the surface of the insulating resin layer (11).

摘要翻译： 倒装芯片型半导体器件在一个表面上设置有多个焊盘电极的半导体芯片（10）。 焊接电极（9）连接到每个焊盘电极，并且金属柱（16b）连接到每个焊料电极（9）。 在其上设置焊盘电极的一侧上的半导体芯片（10）的表面涂覆有绝缘树脂层（11），整个焊盘电极和焊料电极（9）和金属柱（16b）的一部分是 埋在绝缘树脂层（11）中。 金属柱（16b）的剩余部分从绝缘树脂层（11）突出以形成突起。 然后，形成外部焊料电极（13）以覆盖该突起（16b）。 外部焊料电极（13）以矩阵形式布置在绝缘树脂层（11）上。 突起的高度为外部焊料电极（13）的端部与绝缘树脂层（11）的表面之间的距离的7〜50％。

公开(公告)号：EP3361502A1

公开(公告)日：2018-08-15

申请号：EP18155510.3

申请日：2018-02-07

申请人： MediaTek Inc.

发明人： Yu, Ta-Jen ,  Chen, Chi-Yuan ,  Hsu, Wen-Sung

IPC分类号： H01L23/485 ,  H01L23/29

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/06051 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13582 ,  H01L2224/13655 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

公开(公告)号：EP2783393A4

公开(公告)日：2016-03-23

申请号：EP12792149

申请日：2012-06-01

申请人： TEXAS INSTRUMENTS INC

发明人： WEST JEFFREY ALAN

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065

CPC分类号： H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

公开(公告)号：EP2854167A1

公开(公告)日：2015-04-01

申请号：EP14176547.9

申请日：2011-11-23

申请人： ams AG

发明人： Cassidy, Cathal ,  Schrems, Martin ,  Schrank, Franz

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/552

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas and forms an annular cavity surrounding a pillar (105). A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme.

摘要翻译： 该半导体器件包括具有位于的前侧（20），一个基片的金属化（111），其具有上部端子层（22）的半导体基板（10）。 金属化形成通孔从上部终端层，以相对位于前侧处的基板的后侧（21）的后部终端层（13）的基板（23）。 经由包括贯通基板哪个可填充有空气或另一气体和周围的一个支柱（105）的环形腔设计的形式的空隙（101）。 焊球（100）关闭的空隙而不完全填充呼叫它。 各种互连的三维集成是通过该方案提供的。

公开(公告)号：EP2597677A1

公开(公告)日：2013-05-29

申请号：EP11190389.4

申请日：2011-11-23

申请人： austriamicrosystems AG

发明人： Cassidy, Cathal ,  Schrems, Martin ,  Schrank, Franz

IPC分类号： H01L23/48 ,  H01L25/065

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for threedimensional integration is offered by this scheme.