公开(公告)号：EP2250670A2

公开(公告)日：2010-11-17

申请号：EP09726241.4

申请日：2009-02-19

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： SAINT-PATRICE, Damien ,  MARION, François

IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L21/98 ,  H01L23/48 ,  H05K3/32

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/3511 ,  Y10T29/49139 ,  H01L2924/00012

摘要： The invention relates to a component comprising, on one face, a set of conductive inserts to be electrically connected to conductive buried regions of another component, said inserts resting on conductive blocks advantageously produced from a deformable material and positioned at the surface of the component. The surface of the block, which is to come into contact with the insert, has at least one dimension larger than that of the buried region.

公开(公告)号：EP1517364A1

公开(公告)日：2005-03-23

申请号：EP02738780.2

申请日：2002-06-21

申请人： FUJITSU LIMITED

发明人： Chiba, Shuichi, c/o Fujitsu Limited ,  Ishiguri, Masahiko, c/o Fujitsu Limited ,  Murata, Koichi, c/o Fujitsu Limited ,  Watanabe, Eiji, c/o Fujitsu Limited ,  Tamagawa, Michiaki, c/o Fujitsu Tohoku Elec. Ltd. ,  Satoh, Akira, c/o Fujitsu Tohoku Electronics Ltd. ,  Toida, Yasushi, c/o Fujitsu Tohoku Electronics Ltd ,  Misawa, Kazuhiro, c/o Fujitsu Tohoku Elec. Ltd.

IPC分类号： H01L21/60

CPC分类号： H01L24/05 ,  H01L21/2885 ,  H01L22/34 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/19043 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.

摘要翻译： 一种半导体器件包括衬底，形成在衬底上的焊盘电极和形成在焊盘电极上的凸块电极，其中焊盘电极具有不规则缺陷，并且提供覆盖焊盘电极和凸块之间的不规则缺陷的图案 电极。

公开(公告)号：EP1428257A2

公开(公告)日：2004-06-16

申请号：EP02768487.7

申请日：2002-08-12

申请人： DOW CORNING CORPORATION

发明人： LUTZ, Michael, A.

IPC分类号： H01L23/485

CPC分类号： H01L24/12 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00012 ,  H01L2924/00

摘要： An apparatus is disclosed including an electrical conductor and an electrically conductive, compliant bump formed on the electrical conductor. The compliant bump includes an electrically conductive, solderable capping layer and an electrically conductive, compliant body positioned between the solderable capping layer and the electrical conductor . The compliant body electrically couples the solderable capping layer to the electrical conductor. The electrical conductor may be, for example, an input/output (I/0) pad of the apparatus, and the compliant bump may form an electrical terminal of the apparatus. The compliant body forms a mechanically flexible, electrically conductive path between the solderable capping layer and the electrical conductor. The compliant bump deforms elastically when subjected to a force exerted between the solderable capping layer and the electrical conductor, allowing the compliant bump to form a highly reliable connection between the apparatus and an external element. Several embodiments of the compliant bump, and methods for forming the compliant bump, are presented.

公开(公告)号：EP2020023A4

公开(公告)日：2012-09-19

申请号：EP07761307

申请日：2007-04-26

申请人： IBM

发明人： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

公开(公告)号：EP1544913A2

公开(公告)日：2005-06-22

申请号：EP04029836.6

申请日：2004-12-16

申请人： SEIKO EPSON CORPORATION

发明人： Ito, Haruki

IPC分类号： H01L23/31

CPC分类号： H01L23/5226 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/11

摘要： The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wiring with high reliable connection. A semiconductor device (1) comprises a semiconductor element (2) including a plurality of electrodes (9); a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wiring (4a) directed to the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wiring (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wiring (4a) and the second wiring (4b).

摘要翻译： 这里公开的本发明的目的是提供一种半导体器件，该半导体器件可以对应于大尺寸芯片并且具有许多具有高可靠连接的精细布线的外部端子。 半导体装置（1）包括：具有多个电极（9）的半导体元件（2）; 一个或多个树脂层，电连接到电极（9）的多个布线（4），以及电连接到布线（4）的多个外部端子（7）。 多个布线（4）的一部分或全部包括从与电极（9）连接的部分朝向半导体元件（2）的中心（10）的第一布线（4a）， 以及从半导体元件（2）的中心（10）朝向外部区域并耦合到外部端子（7）的第二布线（4b）。 在第一布线（4a）和第二布线（4b）之间形成至少一个树脂层。

公开(公告)号：EP1107307A4

公开(公告)日：2001-12-27

申请号：EP00935668

申请日：2000-06-13

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) is formed to have an opening (3a) corresponding to an electrode pad (2). A projection (4) of resin is then formed on the insulating layer (3). A resist layer is formed to have openings corresponding to the opening (3a), the projection (4) and the area between them. A Cu-plated layer (6) is formed by electrodeposition using the resist layer as a mask.

摘要翻译： 绝缘层（3）形成为具有对应于电极焊盘（2）的开口（3a）。 然后在绝缘层（3）上形成树脂突起（4）。 抗蚀剂层形成为具有对应于开口（3a），突起（4）和它们之间的区域的开口。 通过使用抗蚀剂层作为掩模的电沉积形成镀铜层（6）。

公开(公告)号：EP1107307A8

公开(公告)日：2001-11-21

申请号：EP00935668

申请日：2000-06-13

申请人： FUJIKURA LTD ,  TEXAS INSTRUMENTS JAPAN

发明人： SUZUKI TAKANAO ,  INABA MASATOSHI ,  OMINATO TADANORI ,  KAIZU MASAHIRO ,  KUROSAKA AKIHITO ,  SADAKATA NOBUYUKI ,  MASUMOTO MUTSUMI ,  MASUMOTO KENJI

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60 ,  H01L23/12

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

公开(公告)号：EP2472574A3

公开(公告)日：2017-11-29

申请号：EP11192975.8

申请日：2011-12-12

申请人： Robert Bosch GmbH

发明人： Wolde-Giorgis, Daniel ,  Sentuerk, Tuncay ,  Sueske, Erik ,  Hohenberger, Bernd ,  Klingler, Markus ,  Kalich, Thomas

IPC分类号： H01L21/60 ,  H01L23/482 ,  H01L23/00

CPC分类号： H01L24/83 ,  H01L24/01 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/02125 ,  H01L2224/04026 ,  H01L2224/05573 ,  H01L2224/2745 ,  H01L2224/29005 ,  H01L2224/29007 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/83825 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01063 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/00

摘要： Die Erfindung betrifft ein Verfahren zur Herstellung einer Einpressdiode, die einen Sockel, einen Kopfdraht und einen zwischen den Sockel und den Kopfdraht gelöteten Halbleiterchip aufweist. Zunächst wird ein Halbleiterchip bereitgestellt, auf dessen Ober- und Unterseite jeweils eine bleifreie Legierung mit niedrigem Schmelzpunkt abgeschieden ist. Anschließend erfolgt ein Verbinden des Halbleiterchips mit dem Sockel und dem Kopfdraht mittels Diffusionslöten. Des Weiteren weist die Einpressdiode vorzugsweise elastisch und/oder plastisch verformbare Funktionsschichten auf, die im Betrieb durch Temperaturdifferenzen bedingte Beschädigungen des Halbleiterchips und des Lotes verhindern.

摘要翻译： 本发明涉及一种制造压配二极管的方法，该压配二极管具有插座，头线和焊接在该插座和头线之间的半导体芯片。 首先，提供半导体芯片，在每个的顶部和底部沉积低熔点的无铅合金。 随后，通过扩散焊接将半导体芯片连接到基部和头部导线。 此外，压入式二极管优选具有弹性和/或塑性可变形的功能层，其防止在操作期间由于温度差异而导致半导体芯片和焊料的损坏。

公开(公告)号：EP1544913B1

公开(公告)日：2015-09-02

申请号：EP04029836.6

申请日：2004-12-16

申请人： Seiko Epson Corporation

发明人： Ito, Haruki

IPC分类号： H01L23/31

CPC分类号： H01L23/5226 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/11

摘要： The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wiring with high reliable connection. A semiconductor device (1) comprises a semiconductor element (2) including a plurality of electrodes (9); a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wiring (4a) directed to the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wiring (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wiring (4a) and the second wiring (4b).

公开(公告)号：EP2908337A1

公开(公告)日：2015-08-19

申请号：EP14154852.9

申请日：2014-02-12

申请人： ams AG

发明人： Schrems, Martin ,  Stering, Bernhard ,  Etschmaier, Harald

IPC分类号： H01L23/485 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/485 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a cover layer (2) arranged above the TSV at the main surface, a bump contact (6) arranged on the TSV at the further main surface, and a stress relief feature at the main surface or at the further main surface. The stress relief feature is provided to expose the TSV at least partially to the environment, which can be the ambient air, for instance, or any region of the device lying outside the region occupied by the TSV. The stress relief feature can be a channel (8) in an under-bump metallization (5).

摘要翻译： 该半导体器件包括主表面相对的半导体基片（1）与主表面（10）和另一主表面（11），一个TSV（3）贯穿从主表面的基片的另一主表面上，一个盖 层（2）上面的TSV布置在主表面上，在另外主表面上布置所述TSV的凸块（6）接触，并且在所述主表面或在另外主表面上的应力释放特征。 设置在应力消除功能来至少部分地暴露TSV到环境中，其可以是环境空气，例如，或躺由TSV所占据的区域之外的装置的任何区域。 应力消除功能可以在凸块下金属化是一个信道（8）（5）。