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    APPARATUS AND METHOD IN APPARATUS
    3.
    发明公开
    APPARATUS AND METHOD IN APPARATUS 审中-公开
    装置和方法对设备

    公开(公告)号：EP3017540A4

    公开(公告)日：2017-01-11

    申请号：EP13888804

    申请日：2013-07-04

    申请人： NOKIA TECHNOLOGIES OY

    发明人： LI LEI

    IPC分类号： H03F3/26 ,  H03K17/16

    CPC分类号： H03F3/3001 ,  H03F3/30 ,  H03F3/3022 ,  H03F2003/3003 ,  H03F2200/03 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30081 ,  H03F2203/30111 ,  H03F2203/30114 ,  H03K17/163

    摘要： There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

    APPARATUS AND METHOD IN APPARATUS
    4.
    发明授权
    APPARATUS AND METHOD IN APPARATUS 有权

    公开(公告)号：EP3017540B1

    公开(公告)日：2018-08-22

    申请号：EP13888804.5

    申请日：2013-07-04

    申请人： Nokia Technologies Oy

    发明人： LI, Lei

    IPC分类号： H03F3/26 ,  H03K17/16

    CPC分类号： H03F3/3001 ,  H03F3/30 ,  H03F3/3022 ,  H03F2003/3003 ,  H03F2200/03 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30081 ,  H03F2203/30111 ,  H03F2203/30114 ,  H03K17/163

    摘要： There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

    APPARATUS AND METHOD IN APPARATUS
    6.
    发明公开
    APPARATUS AND METHOD IN APPARATUS 审中-公开
    VORRICHTUNG UND VERFAHREN BEI EINER VORRICHTUNG

    公开(公告)号：EP3017540A1

    公开(公告)日：2016-05-11

    申请号：EP13888804.5

    申请日：2013-07-04

    申请人： Nokia Technologies Oy

    发明人： LI, Lei

    IPC分类号： H03F3/26

    CPC分类号： H03F3/3001 ,  H03F3/30 ,  H03F3/3022 ,  H03F2003/3003 ,  H03F2200/03 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30081 ,  H03F2203/30111 ,  H03F2203/30114 ,  H03K17/163

    摘要： There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

    摘要翻译： 公开了各种方法和装置。 在该方法的一些实施例中，通过第一压摆率调节器将输入信号提供给推挽电路的第一晶体管的输入; 并且输入信号也经由第二压摆率调节器提供给推挽电路的第二晶体管的输入。 输入信号由第一压摆率调整器和第二摆率调节器实现，以在输入信号的幅度增加时第二晶体管截止之后，将第一晶体管导通。 输入信号由第一压摆率调节器和第二转换速率调节器实现，当输入信号的幅度减小时，在第一晶体管截止之后，输入信号切换第二晶体管导通。 在一些实施例中，该装置包括一个包括第一晶体管和第二晶体管的推挽电路; 用于接收输入信号的输入; 第一压摆率调节器，适于将输入信号提供给第一晶体管的输入; 以及适于将输入信号提供给第二晶体管的输入的第二压摆率调节器。 第一压摆率调节器的时间常数取决于输入信号的变化方向，第二转换速率调节器的时间常数取决于输入信号的变化方向。

    Two-stage class AB operational amplifier
    8.
    发明公开
    Two-stage class AB operational amplifier 有权
    Zweistufen-Betriebsverstärkerder Klasse AB

    公开(公告)号：EP2495872A1

    公开(公告)日：2012-09-05

    申请号：EP11156379.7

    申请日：2011-03-01

    申请人： ST-Ericsson SA

    发明人： Nicollini, Germano ,  Pinna, Carlo

    IPC分类号： H03F3/30 ,  H03F3/45

    CPC分类号： H03F3/45264 ,  H03F3/3028 ,  H03F3/45 ,  H03F3/4565 ,  H03F3/45663 ,  H03F2200/297 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/30015 ,  H03F2203/30021 ,  H03F2203/30081 ,  H03F2203/30114 ,  H03F2203/45311 ,  H03F2203/45626 ,  H03F2203/45648 ,  H03F2203/45674 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03H11/1213

    摘要： The invention relates to a two stage class AB operational amplifier (200) for driving a load (L), comprising at least an input stage (201) comprising differential input terminals (IN+, IN-) and an output terminal (N) to provide a driving signal (VN). In addition, the operational amplifier comprises an output stage (202) comprising a first (A) and second (B) input terminals operatively associated to the input stage (201) to be driven on the basis of said driving signal (VN) and a driving circuit (203) operatively interposed between said input stage (201) and the output stage (202). The operational amplifier is characterised in that the driving circuit (203) comprises a first portion (204) comprising at least one resistor (R1) operatively connected between a first reference potential (Vcc) via a first circuitry block (MT, M11) comprising a PMOS transistor (MT) and a second reference potential (GND) via a second circuitry block (M12, MS) comprising a NMOS transistor (MS). The voltage drop (VR1) on said at least a first resistor (R1) is fixed to a value depending on said first (Vcc) and second (GND) reference potentials and the gate-source voltages of said PMOS (MT) and NMOS (MS) transistors, respectively. The driving circuit further comprises a second portion (205) comprising a first resistor (R2) and a second resistor (R2') having first terminals connected one another in a common terminal (P) which is connected to the output terminal (N) of the input stage. Said first resistor (R2) has a second terminal connected the first input terminal (A) of the output stage and said second resistor (R2') has a second terminal connected to the second input terminal (B) of the output stage. Said second terminals (A, B) of the first (R2) and second resistors (R2') are connected to the first reference potential (Vcc) via a third circuitry block (MW, M9) and to the second reference potential (GND) via a fourth circuitry block (M10, MX), respectively. Said third (MW, M9) and fourth (M10, MX) circuitry blocks are arranged to be operatively connected to said first (MT, M11) and second (M12, MS) circuitry blocks, respectively, so that the voltage drop (VR2) between the second terminals (A, B) is substantially equal to the value of the voltage drop (VR1) across said at least one resistor (R1).

    摘要翻译： 本发明涉及用于驱动负载（L）的两级AB运算放大器（200），其包括至少包括差分输入端（IN +，IN-）和输出端（N）的输入级（201），以提供 驱动信号（VN）。 此外，运算放大器包括输出级（202），其包括与基于所述驱动信号（VN）驱动的输入级（201）可操作地相关联的第一（A）和第二（B）输入端，以及 驱动电路（203）可操作地插入在所述输入级（201）和输出级（202）之间。 运算放大器的特征在于，驱动电路（203）包括第一部分（204），第一部分（204）包括经由第一电路块（MT，M11）操作地连接在第一参考电位（Vcc）之间的至少一个电阻器（R1） PMOS晶体管（MT）和第二参考电位（GND），经由包括NMOS晶体管（MS）的第二电路块（M12，MS）。 所述至少第一电阻器（R1）上的电压降（VR1）被固定为取决于所述第一（Vcc）和第二（GND）参考电位的值和所述PMOS（MT）和NMOS（ MS）晶体管。 所述驱动电路还包括第二部分（205），该第二部分包括第一电阻器（R2）和第二电阻器（R2'），所述第一电阻器（R2'）具有在与所述输出端子（N）连接的公共端子（P）中彼此连接的第一端子 输入阶段。 所述第一电阻器（R2）具有与输出级的第一输入端子（A）连接的第二端子，而所述第二电阻器（R2'）具有连接到输出级的第二输入端子（B）的第二端子。 所述第一（R2）和第二电阻（R2'）的所述第二端子（A，B）经由第三电路块（MW，M9）和第二参考电位（GND）连接到第一参考电位（Vcc） 分别经由第四电路块（M10，MX）。 所述第三（MW，M9）和第四（M10，MX）电路块被分别布置成可操作地连接到所述第一（MT，M11）和第二（M12，MS）电路块，使得电压降（VR2） 在第二端子（A，B）之间的电压基本上等于所述至少一个电阻器（R1）上的电压降（VR1）的值。

    TRANSFER GATE CIRCUIT, AND POWER COMBINING CIRCUIT, POWER AMPLIFYING CIRCUIT, TRANSMISSION DEVICE, AND COMMUNICATION DEVICE USING THE TRANSFER GATE CIRCUIT
    9.
    发明公开
    TRANSFER GATE CIRCUIT, AND POWER COMBINING CIRCUIT, POWER AMPLIFYING CIRCUIT, TRANSMISSION DEVICE, AND COMMUNICATION DEVICE USING THE TRANSFER GATE CIRCUIT 审中-公开
    过渡门电路和性能组合切换，电源升压电路，发送装置和通信设备与过渡门电路

    公开(公告)号：EP2461483A1

    公开(公告)日：2012-06-06

    申请号：EP10804152.6

    申请日：2010-03-30

    申请人： Kyocera Corporation

    发明人： NAGAYAMA,Akira ,  FUKUOKA,Yasuhiko ,  IGARASHI,Sadao ,  ISOYAMA,Shinji

    IPC分类号： H03K17/693 ,  H03F3/68

    CPC分类号： H03F3/193 ,  H03F3/245 ,  H03F3/3028 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30114 ,  H03K17/6874 ,  H03K17/693

    摘要： Provided are a transfer gate circuit that has reduced disturbance in an output waveform thereof, a power combining circuit using the transfer gate circuit, and a transmission device and a communication device that use the power combining circuit. The transfer gate circuit includes: output terminals (3, 4) ; a transistor (5) including a drain connected to the output terminal (3); a transistor (6) including a drain connected to the output terminal (4); transistors (7, 8) each including a drain connected to the output terminal (3) and each including a source connected to a ground potential; and transistors (9, 10) each including a drain connected to the output terminal (4) and each including a source connected to the ground potential. In the transfer gate circuit, the transistors (5, 6) include sources to which first and second input signals are input, respectively, the transistor (5) includes a gate to which a signal in phase with the second input signal is input, the transistor (6) includes a gate to which a signal in phase with the first input signal is input, the transistors (7, 9) each include a gate to which a signal in antiphase to the second input signal is input, and the transistors (8, 10) each include a gate to which a signal in antiphase to the first input signal is input.

    摘要翻译： 提供的是一个传输门电路也已在输出波形的扰动减少它们的功率使用传输门电路的组合电路，以及发送装置和通信装置没有使用功率组合电路。 传输门电路包括：输出端子（3,4）; 包括连接到所述输出端子（3）的漏极的晶体管（5）; 包括连接到所述输出端子（4）的漏极的晶体管（6）; 晶体管（7,8）的每个包括连接到所述输出端子（3）的漏极和每个包括连接到接地电位的源; 和晶体管（9，10）的每个包括连接到所述输出端子（4）的漏极，并且每个包括连接到接地电位的源极。 在传输门电路中，晶体管（5,6）包括源到其中第一和第二输入信号被输入，分别，晶体管（5）包括一个栅极连接到哪个相位与所述第二输入信号的信号被输入时， 晶体管（6）包括一个栅极连接到哪个相位与所述第一输入信号的信号被输入时，晶体管（7,9）的每一个包括栅极，以其中在反相位的第二输入信号的信号被输入，并且晶体管（ 8，10）的每一个包括栅极，以其中在反相位的第一输入信号的信号输入。