公开(公告)号：EP1173923B1

公开(公告)日：2008-03-05

申请号：EP01902413.2

申请日：2001-02-05

申请人： NXP B.V.

发明人： BLANKEN, Pieter, G.

IPC分类号： H03F3/45

CPC分类号： H03F3/45704 ,  H03F3/3023 ,  H03F3/45206 ,  H03F3/45475 ,  H03F3/45708 ,  H03F2200/331 ,  H03F2203/45398 ,  H03F2203/45494

摘要： An electronic circuit includes a differential pair (T1, T2) provided with a degeneration device (DGMNS) for degenerating a transconductance of the differential pair (T1, T2), and an auxiliary circuit (B) for supplying a control voltage (U) to a control terminal (CNTRL) of the degeneration device (DGMNS). The auxiliary circuit (B) also accomplishes a DC-biasing of the differential pair (T1, T2). The control voltage (U) and the DC-biasing are such that the transconductance of the differential pair (T1, T2) is virtually independent of the value of the control voltage (U) and virtually independent of the DC-biasing of the differential pair (T1, T2). The auxiliary circuit (B) comprises a further differential pair (T3, T4) provided with a further degeneration device (FDGMNS) for degenerating a transconductance of the further differential pair (T3, T4). The auxiliary circuit (B) is arranged for supplying a further control voltage (UF) to a control terminal (FCNTRL) of the further degeneration device (FDGMNS). The control voltage (U) is dependent on the further control voltage (UF). The further control voltage (UF) and the control voltage (U) can, for instance, be the same voltage. The auxiliary circuit (B) includes a device (B2) for generating a desired current ratio (n) between a first branch (Br1) and a second branch (Br2) of the further differential pair (T3, T4). The auxiliary circuit (B) includes a device (B1) for generating a first DC-voltage (VP) to a first input terminal of the further differential pair (T3, T4), and a second DC-voltage (VM) to a second input terminal of the further differential pair (T3, T4).

公开(公告)号：EP1417752B1

公开(公告)日：2006-07-12

申请号：EP02726934.9

申请日：2002-05-24

申请人： Infineon Technologies AG

发明人： BACH, Elmar ,  BLON, Thomas ,  CYRUSIAN, Sasa ,  FRANCK, Stephen

IPC分类号： H03F3/45

CPC分类号： H03F3/45659 ,  H03F3/45206 ,  H03F2203/45418 ,  H03F2203/45454

摘要： A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

公开(公告)号：EP3314756A1

公开(公告)日：2018-05-02

申请号：EP16722235.5

申请日：2016-05-12

申请人： Huawei Technologies Co., Ltd.

发明人： GRAMEGNA, Giuseppe

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F1/3211 ,  H03F1/302 ,  H03F3/45098 ,  H03F3/45103 ,  H03F3/45206 ,  H03F3/45475 ,  H03F2200/408 ,  H03F2200/447 ,  H03F2200/513 ,  H03F2203/45101 ,  H03F2203/45372 ,  H03F2203/45512 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03F2203/45594 ,  H03F2203/45628 ,  H03F2203/45631 ,  H03F2203/45646 ,  H03F2203/45672 ,  H03F2203/45681 ,  H03F2203/45691 ,  H03F2203/45701 ,  H03F2203/45722

摘要： A circuit comprises: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, coupled in a feed-forward path of the circuit between the circuit input and the circuit output and configured to drive the at least one feedback loop in order to establish a function of the circuit, wherein the feed-forward path of the circuit comprises a second node (Vx) and a first node which are internal nodes of the active element and which are coupled between the circuit input and the circuit output, wherein the first node is configured to have a first voltage, the first voltage being a function of the circuit output, wherein the active element comprises a first voltage drop element coupled between the second node (Vx) and the first node.

公开(公告)号：EP2246977B1

公开(公告)日：2017-05-24

申请号：EP10161454.3

申请日：2010-04-29

申请人： Analog Devices, Inc.

发明人： Tam, Kimo Y.F. ,  Lloyd, Jennifer

IPC分类号： H03F3/50 ,  H03F3/45 ,  H03F3/21 ,  H03F1/02 ,  H03F3/72

CPC分类号： H03F3/505 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45304 ,  H03F2200/168 ,  H03F2200/171 ,  H03F2200/36 ,  H03F2200/39 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/21142 ,  H03F2203/21157 ,  H03F2203/45468 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45656 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/5033

公开(公告)号：EP2246977A3

公开(公告)日：2012-11-14

申请号：EP10161454.3

申请日：2010-04-29

申请人： Analog Devices, Inc.

发明人： Tam, Kimo Y.F. ,  Lloyd, Jennifer

IPC分类号： H03F3/50 ,  H03F3/45 ,  H03F3/21 ,  H03F1/02 ,  H03F3/72

CPC分类号： H03F3/505 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45304 ,  H03F2200/168 ,  H03F2200/171 ,  H03F2200/36 ,  H03F2200/39 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/21142 ,  H03F2203/21157 ,  H03F2203/45468 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45656 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/5033

摘要： In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages (102,104) without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage (112) that maintains the integrity of the frequency response over the complete translator bandwidth.

公开(公告)号：EP2246977A2

公开(公告)日：2010-11-03

申请号：EP10161454.3

申请日：2010-04-29

申请人： Analog Devices, Inc.

发明人： Tam, Kimo Y.F. ,  Lloyd, Jennifer

IPC分类号： H03F3/50 ,  H03F3/45 ,  H03F3/21

CPC分类号： H03F3/505 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45304 ,  H03F2200/168 ,  H03F2200/171 ,  H03F2200/36 ,  H03F2200/39 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/21142 ,  H03F2203/21157 ,  H03F2203/45468 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45656 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/5033

摘要： In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages (102,104) without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage (112) that maintains the integrity of the frequency response over the complete translator bandwidth.

摘要翻译： 在本发明的实施例中，常规电压转换器中的低频响应差，低速，高成本和高功耗的问题通过在两个并联级中分别处理输入信号的高频和低频分量来解决（102,104 ），而不使用大的无源组件或慢速设备。 在输出端，经处理的高频和低频分量在组合级（112）无缝地合并，该组合级保持了整个转换器带宽上的频率响应的完整性。

公开(公告)号：EP1417752A2

公开(公告)日：2004-05-12

申请号：EP02726934.9

申请日：2002-05-24

申请人： Infineon Technologies AG

发明人： BACH, Elmar ,  BLON, Thomas ,  CYRUSIAN, Sasa ,  FRANCK, Stephen

IPC分类号： H03F3/45

CPC分类号： H03F3/45659 ,  H03F3/45206 ,  H03F2203/45418 ,  H03F2203/45454

摘要： A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

公开(公告)号：EP1173923A1

公开(公告)日：2002-01-23

申请号：EP01902413.2

申请日：2001-02-05

申请人： Koninklijke Philips Electronics N.V.

发明人： BLANKEN, Pieter, G.

IPC分类号： H03F3/45

CPC分类号： H03F3/45704 ,  H03F3/3023 ,  H03F3/45206 ,  H03F3/45475 ,  H03F3/45708 ,  H03F2200/331 ,  H03F2203/45398 ,  H03F2203/45494

摘要： An electronic circuit includes a differential pair (T1, T2) provided with a degeneration device (DGMNS) for degenerating a transconductance of the differential pair (T1, T2), and an auxiliary circuit (B) for supplying a control voltage (U) to a control terminal (CNTRL) of the degeneration device (DGMNS). The auxiliary circuit (B) also accomplishes a DC-biasing of the differential pair (T1, T2). The control voltage (U) and the DC-biasing are such that the transconductance of the differential pair (T1, T2) is virtually independent of the value of the control voltage (U) and virtually independent of the DC-biasing of the differential pair (T1, T2). The auxiliary circuit (B) comprises a further differential pair (T3, T4) provided with a further degeneration device (FDGMNS) for degenerating a transconductance of the further differential pair (T3, T4). The auxiliary circuit (B) is arranged for supplying a further control voltage (UF) to a control terminal (FCNTRL) of the further degeneration device (FDGMNS). The control voltage (U) is dependent on the further control voltage (UF). The further control voltage (UF) and the control voltage (U) can, for instance, be the same voltage. The auxiliary circuit (B) includes a device (B2) for generating a desired current ratio (n) between a first branch (Br1) and a second branch (Br2) of the further differential pair (T3, T4). The auxiliary circuit (B) includes a device (B1) for generating a first DC-voltage (VP) to a first input terminal of the further differential pair (T3, T4), and a second DC-voltage (VM) to a second input terminal of the further differential pair (T3, T4).