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    DELTA-SIGMA MODULATOR WITH DELTA-SIGMA TRUNCATOR AND ASSOCIATED METHOD FOR REDUCING LEAKAGE ERRORS OF DELTA-SIGMA MODULATOR
    2.
    发明公开
    DELTA-SIGMA MODULATOR WITH DELTA-SIGMA TRUNCATOR AND ASSOCIATED METHOD FOR REDUCING LEAKAGE ERRORS OF DELTA-SIGMA MODULATOR 审中-公开
    具有DELTA-SIGMA调制器的DELTA-SIGMA调制器以及用于减少DELTA-SIGMA调制器的泄漏错误的相关方法

    公开(公告)号：EP3280055A1

    公开(公告)日：2018-02-07

    申请号：EP17182826.2

    申请日：2017-07-24

    Applicant: MediaTek Inc.

    Inventor： WENG, Chan-Hsiang ,  LO, Tien-Yu

    IPC: H03M3/04 ,  H03M1/06

    CPC classification number: H03M3/426 ,  H03M1/00 ,  H03M1/066 ,  H03M1/12 ,  H03M3/30 ,  H03M3/428 ,  H03M3/436 ,  H03M3/454

    Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

    Abstract translation: Δ-Σ调制器包括接收电路，环路滤波器模块，量化器，Δ-Σ截断器，数字滤波器模块和输出电路。 接收电路被设置用于接收反馈信号和输入信号以生成求和信号。 环路滤波器模块用于对求和信号进行滤波以产生滤波后的和信号。 量化器用于根据滤波后的和信号生成第一数字信号。 Δ-Σ截断器被设置用于截断第一数字信号以产生第二数字信号。 数字滤波器模块用于对第一数字信号和第二数字信号进行滤波，以分别生成滤波后的第一数字信号和滤波后的第二数字信号。 输出电路用于根据滤波后的第一数字信号和滤波后的第二数字信号生成输出信号。

    Analog-to-digital converter
    3.
    发明公开
    Analog-to-digital converter 有权
    模拟Digitalumsetzer

    公开(公告)号：EP2592756A1

    公开(公告)日：2013-05-15

    申请号：EP11189057.0

    申请日：2011-11-14

    Applicant: Telefonaktiebolaget L M Ericsson AB (Publ)

    Inventor： Anderson, Martin ,  Sundström, Lars

    IPC: H03M3/02

    CPC classification number: H03M3/396 ,  H03M3/374 ,  H03M3/436 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464 ,  H04B1/16 ,  H04W88/02 ,  H04W88/08

    Abstract: A continuous-time ΣΔ-ADC (1) is disclosed. It comprises a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ΔΣ-ADC (1) at sample instants nT, where n is an integer sequence index and T is a sampling period, based on an analog input signal to the quantizer (5). Furthermore, the ΔΣ-ADC (1) comprises one or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5). Moreover, the ΔΣ-ADC (1) comprises a continuous-time analog network (20) arranged to generate the analog input signal to the quantizer (5) based on the feedback signal(s) from the one or more DACs (10a-b) and an analog input signal to the ΔΣ-ADC (1). At least one DAC (10b) of the one or more DACs (10b) comprises two switched-capacitor DACs (40, 50) arranged to operate on the same input but with a mutual delay in time. A corresponding radio receiver circuit (100), a corresponding integrated circuit (200), and a corresponding radio communication apparatus (300, 400) are also disclosed.

    Abstract translation: 公开了连续时间“-ADC（1）”。 它包括一个采样量化器（5），被配置为产生在样本时刻nT处的“-ADC（1）”的数字输出信号的样本y（n），其中n是整数序列索引，T是采样周期 对量化器（5）的模拟输入信号。 此外，“-ADC（1）”包括一个或多个DAC（10a-b），每个DAC（10a-b）被布置为基于由采样的量化器（5）生成的数字输出信号的采样来产生模拟反馈信号。 此外，“-ADC（1）包括连续时间模拟网络（20），其被布置为基于来自所述一个或多个DAC（10a-）的反馈信号来产生到量化器（5）的模拟输入信号， b）和到“£-ADC（1）”的模拟输入信号。 一个或多个DAC（10b）的至少一个DAC（10b）包括布置成在相同输入上操作但具有相互延迟的两个开关电容器DAC（40,50）。 还公开了相应的无线电接收器电路（100），相应的集成电路（200）和相应的无线电通信装置（300,400）。

    SIGMA-DELTA MODULATOR
    4.
    发明公开
    SIGMA-DELTA MODULATOR 有权
    SIGMA-DELTA调制器

    公开(公告)号：EP2340613A1

    公开(公告)日：2011-07-06

    申请号：EP09744470.7

    申请日：2009-10-21

    Applicant: NXP B.V.

    Inventor： VAN VELDHOVEN, Robert Henrikus Margaretha ,  BREEMS, Lucien Johannes ,  RUTTEN, Robert

    IPC: H03M3/00 ,  H03M1/06

    CPC classification number: H03M3/368 ,  H03M3/436

    Abstract: A sigma-delta modulator (400) 400, 500, 600) for converting an input signal (X(s)) (X(s)) to a quantized output signal (Y(z)) (Y(z)), in which a feedback loop is provided between a filter (402) and a quantizer (403) of the modulator, the feedback loop configured to reduce quantization errors from the modulator by filtering and subtracting quantization noise fed back to an input of the quantizer (403).

    QUADRATURE SIGNAL CONVERSION DEVICE
    5.
    发明公开
    QUADRATURE SIGNAL CONVERSION DEVICE 失效
    装置转换的信号的正交

    公开(公告)号：EP0763278A2

    公开(公告)日：1997-03-19

    申请号：EP96904247.0

    申请日：1996-03-18

    Applicant: PHILIPS ELECTRONICS N.V.

    Inventor： STIKVOORT, Eduard, Ferdinand

    IPC: H03C3 ,  H03D3 ,  H03M3 ,  H04B1 ,  H04L27

    CPC classification number: H03C3/40 ,  H03D3/007 ,  H03H2011/0494 ,  H03M3/40 ,  H03M3/422 ,  H03M3/436 ,  H03M3/456 ,  H04L27/2332

    Abstract: In a receiver two sigma delta modulators (13, 19) are used to convert a pair of analog quatradure signals into digital quadrature signals. In such sigma delta modulators the quantisation noise is shifted into a frequency region in which no signal is present. In order to improve the noise reduction without increasing the order of the filters (15, 17) a cross coupling between the filters (15, 17) is made. Due to this cross coupling it is possible to obtain complex poles and zeros in the noise transfer function which do not have to appear in complex conjugate pairs, resulting in an increase of the noise suppression in one specified frequency range.

    FEED-FORWARD OPERATIONAL AMPLIFIER NOISE CANCELLATION TECHNIQUE AND ASSOCIATED FILTER AND DELTA-SIGMA MODULATOR
    6.
    发明公开
    FEED-FORWARD OPERATIONAL AMPLIFIER NOISE CANCELLATION TECHNIQUE AND ASSOCIATED FILTER AND DELTA-SIGMA MODULATOR 审中-公开
    前馈运算放大器噪声消除技术及相关滤波器和DELTA-SIGMA调制器

    公开(公告)号：EP3293879A2

    公开(公告)日：2018-03-14

    申请号：EP17184344.4

    申请日：2017-08-01

    Applicant: MediaTek Inc.

    Inventor： TSAI, Hung-Chieh

    IPC: H03F1/26 ,  H03F1/32 ,  H03F3/45

    CPC classification number: H03M3/368 ,  H03F1/26 ,  H03F1/3223 ,  H03F1/3229 ,  H03F1/3247 ,  H03F3/45 ,  H03F3/45475 ,  H03F2200/411 ,  H03F2203/45116 ,  H03G3/20 ,  H03M3/422 ,  H03M3/436 ,  H03M3/458

    Abstract: A circuit includes a first amplifying stage, a noise extraction circuit and a noise cancellation circuit. The first amplifying stage is arranged for receiving an input signal to generate an amplified input signal. The noise extraction circuit is coupled to the first amplifying stage, and is arranged for receiving at least the amplified input signal to generate a noise signal associated with noise components of the amplified input signal. The noise cancellation circuit is coupled to the first amplifying stage and the noise extraction circuit, and is arranged for cancelling noise components of the amplified input signal by using the noise signal generated by the noise extraction circuit, to generate a noise-cancelled amplified input signal.

    Abstract translation: 电路包括第一放大级，噪声提取电路和噪声消除电路。 第一放大级被安排用于接收输入信号以生成放大的输入信号。 噪声提取电路耦合到第一放大级，并且被布置用于至少接收放大的输入信号以生成与放大的输入信号的噪声分量相关联的噪声信号。 噪声消除电路耦合到第一放大级和噪声提取电路，并且被布置为通过使用由噪声提取电路生成的噪声信号来消除放大的输入信号的噪声成分，以生成噪声消除的放大输入信号 。

    SAMPLING/QUANTIZATION CONVERTERS
    7.
    发明公开
    SAMPLING/QUANTIZATION CONVERTERS 审中-公开
    扫描/数量化转换器

    公开(公告)号：EP2446538A1

    公开(公告)日：2012-05-02

    申请号：EP10734856.7

    申请日：2010-06-26

    Applicant: Pagnanelli, Christopher ,  Syntropy Systems

    Inventor： Pagnanelli, Christopher ,  Syntropy Systems

    IPC: H03M3/02 ,  H03M3/04

    CPC classification number: H03M3/468 ,  H03M3/436

    Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple quantization-noise-shaping continuous-time filters, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter.

    CODER APPARATUS FOR RESONANT POWER CONVERSION AND METHOD
    8.
    发明公开
    CODER APPARATUS FOR RESONANT POWER CONVERSION AND METHOD 审中-公开
    编码器的响应功率转换器和方法

    公开(公告)号：EP1488336A4

    公开(公告)日：2006-02-15

    申请号：EP03713862

    申请日：2003-03-04

    Applicant: ST MICROELECTRONICS NV

    Inventor： NORDSWORTHY STEVEN R

    IPC: H03M3/02 ,  H03M3/04 ,  H04B1/04 ,  G06F17/20

    CPC classification number: H04B1/04 ,  H03M3/332 ,  H03M3/424 ,  H03M3/436

    Abstract: An Nth-order shaping coder with multi-level quantization and dithered quantizer. The coder (500) is inherently stable and produces a purely white quantization error spectrum. In one exemplary embodiment, the coder is first order, and an improved dither scheme is employed including applying a M-times, e.g. M=2, sample-and-hold to the dither sequence, effectively holding a constant dither for multiple clock cycles. This advantageously results in a reduction of instances where the quantizer jumps over two quantization intervals in one clock cycle without first passing through zero for one clock cycle. Methods for implementing the shaping coder are also disclosed.

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