利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.011 秒)

    A process and a device for speed adaptation for integrated services digital network (ISDN)
    4.
    发明公开
    A process and a device for speed adaptation for integrated services digital network (ISDN) 失效
    用于集成服务数字网络（ISDN）的速度适配的过程和单一集成设备

    公开(公告)号：EP0426623A3

    公开(公告)日：1992-08-19

    申请号：EP90830469.4

    申请日：1990-10-22

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Dell'Oro, Annalisa ,  Corazzo, Fulvio ,  Tognini, Pietro ,  Conegian, Stefano

    IPC分类号： H04Q11/04 ,  H04L5/24 ,  H04L25/36

    CPC分类号： H04Q11/0471 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13209 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/13297 ,  H04Q2213/13305 ,  H04Q2213/1331 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/1336 ,  H04Q2213/13361 ,  H04Q2213/13362

    摘要： The process of synchronization and decomposition of asynchronous frames organized with octet-rows of bits, for the adaptation of speed carried out by an intermediate reception block for adaptation of speed of an integrated device for the adaptation of synchronous and asynchronous terminals according to the CCITT V.110 standard to an Integrated Services Digital Network, is carried out by storing one octet at a time in an 8-bit shift register (RSC8) and by using counters (RSA,RSB,RSC8) in order to store the current position of each octet within a respective asynchronous frame and by recognizing by means of other counters (CT80,CTNFR) the relevant bits of each octet, which are stored and switched to the respective elements for management and for control of the serial flow of data from the network to the terminal. From this, an architecture is derived, which is particularly simplified by means of the redimensioning of the registers which, instead of storing an entire frame, have to store only one octet at a time. Also, the delay undergone by the data in transfer by means of the block is reduced to the delay necessary for the shifting of a single octet. In fact, there will never be more than two octets at a time contained within the block instead of two frames or one, as would be necessary according to an architecture of conventional type. Two PLAs (RS2,RS3), each functioning with its own clock (CK0,CK1), manage and control the synchronization, the decomposition of the frames into octets and the addressing of the bits and, respectively, the flow of the data in input to and in output from the block in relation to said standard.

    A process and a device for speed adaptation for integrated services digital network (ISDN)
    6.
    发明公开
    A process and a device for speed adaptation for integrated services digital network (ISDN) 失效
    过程和用于速度适应一个单片集成器件为综合业务数字通信网（ISDN）。

    公开(公告)号：EP0426623A2

    公开(公告)日：1991-05-08

    申请号：EP90830469.4

    申请日：1990-10-22

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Dell'Oro, Annalisa ,  Corazzo, Fulvio ,  Tognini, Pietro ,  Conegian, Stefano

    IPC分类号： H04Q11/04 ,  H04L5/24 ,  H04L25/36

    CPC分类号： H04Q11/0471 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13209 ,  H04Q2213/13214 ,  H04Q2213/13216 ,  H04Q2213/13297 ,  H04Q2213/13305 ,  H04Q2213/1331 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/1336 ,  H04Q2213/13361 ,  H04Q2213/13362

    摘要： The process of synchronization and decomposition of asynchronous frames organized with octet-rows of bits, for the adaptation of speed carried out by an intermediate reception block for adaptation of speed of an integrated device for the adaptation of synchronous and asynchronous terminals according to the CCITT V.110 standard to an Integrated Services Digital Network, is carried out by storing one octet at a time in an 8-bit shift register (RSC8) and by using counters (RSA,RSB,RSC8) in order to store the current position of each octet within a respective asynchronous frame and by recognizing by means of other counters (CT80,CTNFR) the relevant bits of each octet, which are stored and switched to the respective elements for management and for control of the serial flow of data from the network to the terminal. From this, an architecture is derived, which is particularly simplified by means of the redimensioning of the registers which, instead of storing an entire frame, have to store only one octet at a time. Also, the delay undergone by the data in transfer by means of the block is reduced to the delay necessary for the shifting of a single octet. In fact, there will never be more than two octets at a time contained within the block instead of two frames or one, as would be necessary according to an architecture of conventional type. Two PLAs (RS2,RS3), each functioning with its own clock (CK0,CK1), manage and control the synchronization, the decomposition of the frames into octets and the addressing of the bits and, respectively, the flow of the data in input to and in output from the block in relation to said standard.

    摘要翻译： 同步，并与比特的八位字节行组织的，对速度的通过在中间接收块开展为集成器件的速度的适配为同步和异步终端的适配雅丁到CCITT V中的适应异步帧的分解过程中 0.110标准对综合业务数字网，是由在8位的移位寄存器一个时间存储一个字节，通过以存储respectivement异步帧内的每个八位位组的当前位置使用计数器以及通过认识开展 其它计数器的手段每个八位位组的相关位，其存储与切换到respectivement元素管理和数据从网络到终端的串行流的控制。 由此，以体系结构衍生的，在所有其特别通过其中，而不是存储到整个帧的寄存器的redimensioning得以简化，具有只存储一个八位字节一次。 因此，通过将数据在由块的方式传输经受的延迟减少到延迟必需的单个八位字节的偏移。 实际上，永远不会有在包含在块而不是两个帧或一个内的时间多于两个八位字节，如有必要gemäß在传统类型的体系结构。 两个PLA中，每个都有其自己的时钟运行，管理和控制的同步，帧入八位位组的分解和比特分别从块相对于寻址和，中，数据的输入流并在输出到 该标准。