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1.发明专利
公开(公告)号：JP4255733B2
公开(公告)日：2009-04-15
申请号：JP2003105688
申请日：2003-04-09
申请人： ソニー株式会社
CPC分类号： G11C27/024 , G11C27/026 , H03F3/45089 , H03F2203/45626 , H03F2203/45631 , H03F2203/45651 , H03F2203/45696 , H03F2203/45702 , H03F2203/45726 , H03K5/2481 , H03K5/249 , H03M1/142 , H03M1/206 , H03M1/365
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公开(公告)号：JP2008278493A
公开(公告)日：2008-11-13
申请号：JP2008119095
申请日：2008-04-30
发明人： KIM HYOUNG-RAE
CPC分类号： H03F3/45179 , H03F3/3022 , H03F2200/297 , H03F2200/456 , H03F2203/30015 , H03F2203/45292 , H03F2203/45318 , H03F2203/45364 , H03F2203/45626
摘要： PROBLEM TO BE SOLVED: To provide an adaptive biasing input stage and amplifiers including the same.
SOLUTION: The adaptive biasing input stage includes pairs of differentially coupled amplifying and sensing FETs having gates with differential inputs applied thereon. In addition, a static current source is coupled to the sources of the amplifying and sensing FETs at a predetermined node. Also, current mirrors are coupled to the sensing FETs for forming loop mechanisms that increases the current through the predetermined node, when the differential inputs have a non-zero difference.
COPYRIGHT: (C)2009,JPO&INPIT摘要翻译： 要解决的问题：提供自适应偏置输入级和包括其的放大器。 解决方案：自适应偏置输入级包括具有施加差分输入的门的差分耦合放大和感测FET对。 此外，静态电流源耦合到预定节点处的放大和感测FET的源极。 此外，当差分输入具有非零差时，电流镜耦合到感测FET，用于形成环路机构，其增加通过预定节点的电流。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP5503671B2
公开(公告)日：2014-05-28
申请号：JP2012016887
申请日：2012-01-30
申请人： 株式会社半導体理工学研究センター
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/3028 , H03F3/45183 , H03F2203/30021 , H03F2203/45244 , H03F2203/45454 , H03F2203/45626
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公开(公告)号：JP2007104647A
公开(公告)日：2007-04-19
申请号：JP2006240615
申请日：2006-09-05
发明人： LEE YOUN JOONG , CHOI WON TAE , PARK CHAN WOO , KIM BYUNG HOON
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03F3/45219 , H03F3/3022 , H03F3/45183 , H03F2203/45118 , H03F2203/45248 , H03F2203/45366 , H03F2203/45536 , H03F2203/45626
摘要： PROBLEM TO BE SOLVED: To provide an output buffer circuit in which a slew rate increasing part constituted of a switching element is added, so that an output voltage having a high slew rate is obtained even through a smaller amount of a bias current than that required in a conventional output buffer, thereby preventing much power from being consumed. SOLUTION: The output buffer circuit including a compensation capacitive load Cc comprises: input terminals 501a-501e applying differential input voltage signals to two input terminals; an output terminal 502 that increases a gain of the differential input voltages; a current source 503 that biases the output terminal; and a slew rate increasing part 504 which is connected to the output terminal and the compensation capacitive load, and includes a switching element to increase a slew rate of the output buffer circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译： 要解决的问题：为了提供一种输出缓冲电路，其中添加了由开关元件构成的转换速率增加部分，使得即使通过较小量的偏置电流也获得具有高压摆率的输出电压 比常规输出缓冲器中所需的那样大，从而防止消耗大量功率。 解决方案：包括补偿容性负载Cc的输出缓冲电路包括：将差分输入电压信号施加到两个输入端的输入端501a-501e; 输出端子502，其增加差分输入电压的增益; 偏置输出端的电流源503; 以及连接到输出端子和补偿电容性负载的转换速率增加部分504，并且包括用于增加输出缓冲器电路的转换速率的开关元件。 版权所有（C）2007，JPO＆INPIT
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5.发明专利
公开(公告)号：JP2012257273A
公开(公告)日：2012-12-27
申请号：JP2012162693
申请日：2012-07-23
发明人： HEIG DAVAG , DONWHANG THEO , MANUE MISHRA
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/52 , H03F1/523 , H03F3/303 , H03F2203/30015 , H03F2203/30084 , H03F2203/30117 , H03F2203/45244 , H03F2203/45626 , H03F2203/45732
摘要： PROBLEM TO BE SOLVED: To provide a high-swing operational amplifier using an adaptive biasing output stage without increasing the processing cost.SOLUTION: An output stage 123 includes two transistors (switching transistor T3 and biasing transistor T4) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor T1 and biasing transistor T2) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors T4, T2 reduces the maximum voltage dropped across the transistors T3, T4, thereby allowing the transistors T1 to T4 to have lower breakdown voltages than VDDA.
摘要翻译： 要解决的问题：提供使用自适应偏置输出级的高摆幅运算放大器，而不增加处理成本。 解决方案：输出级123包括串联耦合在VDDA节点和输出节点之间的上拉电流路径中的两个晶体管（开关晶体管T3和偏置晶体管T4），并且还包括两个晶体管（开关晶体管T1和偏置晶体管T4） T2）串联耦合在输出节点和接地节点之间的下拉电流路径中。 提供偏置晶体管T4，T2降低了晶体管T3，T4两端下降的最大电压，从而允许晶体管T1至T4具有比VDDA更低的击穿电压。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2008277889A
公开(公告)日：2008-11-13
申请号：JP2007115713
申请日：2007-04-25
发明人： SUZUKI YASUFUMI
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F3/3022 , H03F2203/30015 , H03F2203/45318 , H03F2203/45626
摘要： PROBLEM TO BE SOLVED: To solve the following problem: an output current varies owing to variation in-phase input potential and an operating speed decreases as a result.
SOLUTION: An amplifying circuit according to the present invention has a differential output stage and a differential input stage, the differential output stage has first and second current paths connected between first and second power sources and outputting differential signals, wherein the first current path has a first resistance element between the first power source and a first node , first and second transistors between the first node and a second node, and a second resistance element between the second node and second power source, and wherein the second current path has a third resistance element between the first power source and a third node, third and fourth transistors between the third node and a fourth node, and a fourth resistance element between the fourth node and second power source, and wherein gates of the first, second, third, and fourth transistors are connected to the fourth, third, second, and first nodes, respectively and an output current of the differential input stage is connected to the first and third nodes.
COPYRIGHT: (C)2009,JPO&INPIT摘要翻译： 要解决的问题：为了解决以下问题：由于相位输入电位的变化，输出电流变化，结果运行速度降低。 解决方案：根据本发明的放大电路具有差分输出级和差分输入级，差分输出级具有连接在第一和第二电源之间的第一和第二电流路径，并输出差分信号，其中第一电流 路径在第一电源和第一节点之间具有第一电阻元件，第一节点和第二节点之间的第一和第二晶体管，以及第二节点和第二电源之间的第二电阻元件，并且其中第二电流路径具有 第一电源和第三节点之间的第三电阻元件，第三节点和第四节点之间的第三和第四晶体管，以及第四节点和第二电源之间的第四电阻元件， 第三和第四晶体管分别连接到第四，第三，第二和第一节点以及差分的输出电流 输入级连接到第一和第三节点。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2003529266A
公开(公告)日：2003-09-30
申请号：JP2001571553
申请日：2001-03-28
发明人： シュティマ，ヤロ , シュレーディンガー，カール
CPC分类号： H03F3/3037 , H03F3/45183 , H03F2203/45508 , H03F2203/45626
摘要： (57)【要約】 本発明は、電子出力モジュール、特には、アナログおよびデジタル高周波数回路に使用されるＣＭＯＳ−ＬＶＤＳ水準（ＬＶＤＳ−低電圧差動信号）用の電子出力モジュールに関するものである。 上記出力モジュールは、第１接続によって電流源（Ｔ８）に接続されており、制御接続によって入力端子に接続されている第１および第２トランジスタ（Ｔ６，Ｔ７）を備えている。 第３および第４トランジスタ（Ｔ４，Ｔ５）は、第１接続によって供給電圧電位（ＶＯＯ）に接続されており、第２接続によって第１および第２トランジスタ（Ｔ６，Ｔ７）の第２接続と出力端子とに接続されており、制御接続によって変流された入力信号に接続されている。
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公开(公告)号：JP2013157805A
公开(公告)日：2013-08-15
申请号：JP2012016887
申请日：2012-01-30
发明人： HIROSE TETSUYA , OSAKI YUJI , TSURUYA YUMIKO , KOBAYASHI OSAMU
CPC分类号： H03F3/45179 , H03F1/0261 , H03F3/3028 , H03F3/45183 , H03F2203/30021 , H03F2203/45244 , H03F2203/45454 , H03F2203/45626
摘要： PROBLEM TO BE SOLVED: To provide a differential amplification circuit that can operate at higher speed and on lower power than the prior art.SOLUTION: The differential amplification circuit having a differential operational amplifier including a differential pair circuit and operating on a constant bias current supplied from a bias current source circuit includes: a bias current generation circuit including a current monitor circuit for detecting two currents flowing through the differential pair circuit in response to differential input voltages input into the differential pair circuit, and detecting the lower of the two currents as a monitor current for a differential voltage of the differential input voltages, a current comparison circuit for comparing the monitor current with the constant bias current supplied from the bias current source circuit, and outputting a voltage corresponding to the result of comparison, and a current amplification circuit for amplifying the voltage corresponding to the result of comparison, and controlling a current flowing to the differential pair circuit on the basis of the amplified voltage. The bias current generation circuit performs negative feedback adaptive control such that the bias current flowing to the differential pair circuit increases with decreasing monitor current.
摘要翻译： 要解决的问题：提供可以以比现有技术更高的速度和更低的功率工作的差分放大电路。解决方案：差分放大电路具有差分运算放大器，其包括差分对电路并且在提供的恒定偏置电流上工作 偏置电流源电路包括：偏置电流产生电路，包括电流监测电路，用于响应于输入到差分对电路中的差分输入电压检测流过差分对电路的两个电流，并且检测两个电流中的较低的电流 用于差分输入电压的差分电压的监视电流，用于将监视电流与从偏置电流源电路提供的恒定偏置电流进行比较的电流比较电路，以及输出与比较结果相对应的电压，以及电流放大 放大电压相关电路 涉及比较的结果，并且基于放大的电压来控制流向差分对电路的电流。 偏置电流产生电路执行负反馈自适应控制，使得流到差分对电路的偏置电流随着监视电流的减小而增加。
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公开(公告)号：JP4695621B2
公开(公告)日：2011-06-08
申请号：JP2007115713
申请日：2007-04-25
申请人： ルネサスエレクトロニクス株式会社
发明人： 康文 鈴木
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F3/3022 , H03F2203/30015 , H03F2203/45318 , H03F2203/45626
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公开(公告)号：JP2010288266A
公开(公告)日：2010-12-24
申请号：JP2010099067
申请日：2010-04-22
发明人： ISODA NAOKI
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/3022 , H03F3/45645 , H03F2203/30015 , H03F2203/45134 , H03F2203/45404 , H03F2203/45421 , H03F2203/45422 , H03F2203/45512 , H03F2203/45514 , H03F2203/45534 , H03F2203/45544 , H03F2203/45551 , H03F2203/45616 , H03F2203/45626 , H03F2203/45702
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in performing common mode feedback operation in a fully-differential amplifier circuit.
SOLUTION: The fully-differential amplifier circuit includes: a differential amplifier configured to differentially amplify first and second input signals forming an input differential pair to generate first and second intermediate signals forming a pair; and first and second class AB amplifiers configured to amplify the first and second intermediate signals to generate first and second output signals, respectively. The first and second output signals form an output differential pair, the first class AB amplifier amplifies the first intermediate signal based on a reference voltage adjusted by a first feedback signal that is a common mode component of the first output signal and the second output signal. The second class AB amplifier amplifies the second intermediate signal based on a reference voltage adjusted by a second feedback signal that is a common mode component of the first output signal and the second output signal.
COPYRIGHT: (C)2011,JPO&INPIT摘要翻译： 要解决的问题：为了降低在全差分放大器电路中执行共模反馈操作的功耗。 解决方案：全差分放大器电路包括：差分放大器，被配置为差分放大形成输入差分对的第一和第二输入信号，以产生形成一对的第一和第二中间信号; 以及配置成放大第一和第二中间信号以分别产生第一和第二输出信号的第一和第二AB类放大器。 第一和第二输出信号形成输出差分对，第一类AB放大器基于由作为第一输出信号和第二输出信号的共模分量的第一反馈信号调整的参考电压放大第一中间信号。 第二类AB放大器基于由作为第一输出信号和第二输出信号的共模分量的第二反馈信号调整的参考电压放大第二中间信号。 版权所有（C）2011，JPO＆INPIT
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