SiC SEMICONDUCTOR COMPONENT COMPRISING PN JUNCTION WITH VOLTAGE ABSORBING EDGE
    8.
    发明专利
    SiC SEMICONDUCTOR COMPONENT COMPRISING PN JUNCTION WITH VOLTAGE ABSORBING EDGE 审中-公开
    具有电压吸收边缘的PN结的SiC半导体元件

    公开(公告)号:JP2013062545A

    公开(公告)日:2013-04-04

    申请号:JP2013000103

    申请日:2013-01-04

    摘要: PROBLEM TO BE SOLVED: To prevent voltage breakdown in an edge due to a high electric field, by implanting electric charge into a zone of a junction termination extension in a semiconductor device comprising a pn junction such that effective charge density decreases stepwise toward the edge.SOLUTION: An embodiment comprises a pn junction. Both a p-conducting layer 3 and an n-conducting layer 2 of the pn junction constitute doped silicon carbide layers. In an edge of a highly doped conducting layer of the pn junction, electric charge implantation is repeated such that the width of a mask 10 decreases stepwise toward the outermost edge, that is, total charge or effective surface charge density decreases stepwise from an initial value at the main pn junction to zero or almost zero at the outermost edge of the junction in a radial direction from the central part of the junction toward the outermost edge.

    摘要翻译: 要解决的问题:为了防止由于高电场导致的边缘中的电压击穿,通过在包括pn结的半导体器件中将电荷注入到连接端接延伸区域中,使得有效电荷密度逐步朝向 边缘。 解决方案:实施例包括pn结。 pn结的p导电层3和n导电层2均构成掺杂的碳化硅层。 在pn结的高度掺杂的导电层的边缘中,重复电荷注入,使得掩模10的宽度朝向最外边缘逐步减小,即总电荷或有效表面电荷密度从初始值逐步降低 在主pn结处,在从接合部的中心部分到最外边缘的径向方向的接合部的最外边缘处为零或几乎为零。 版权所有(C)2013,JPO&INPIT