摘要:
구현예는 규소 원자 층이 표면 상에 노출되는 일면 및 탄소 원자 층이 표면 상에 노출되는 타면을 포함하고, 나노인덴테이션 테스트에 따라, 삼각뿔 형상의 인덴터가 탄화규소 웨이퍼에 압입이 시작될 때부터 10 mN에 도달할 때까지 하중(y)에 따른 압입량(x)을 y=ax 2 +bx+c 꼴로 회귀한 2차 다항식에서, 상기 a는 0.37 내지 0.6이고, 상기 b는 10 내지 33인, 탄화규소 웨이퍼 및 이를 적요한 반도체 소자에 관한 것이다.
摘要:
본 발명은 고주파 응답 특성이 우수하고, 상대적으로 저온에서 공정이 진행되어 유리 또는 플라스틱과 같은 녹는점이 낮은 재질에서 직접 제조할 수 있는 이차원 반도체 물질을 이용한 수직형 쇼트키 다이오드 및 이의 제조방법에 관한 것으로, 상기한 수직형 쇼트키 다이오드는 금속으로 형성되는 오믹 접촉층(100), 상기 오믹 접촉층(100)의 일면에 이차원 전이금속 화합물로 형성되는 이차원 반도체층(200), 상기 이차원 반도체층(200)의 일면에 형성되는 쇼트키 접촉층(300) 및 상기 오믹 접촉층(100)의 타면 또는 상기 쇼트키 접촉층(300)의 일면에 형성되는 부도체층(10)을 포함하는 것을 특징으로 한다.
摘要:
Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate (100') through an opening in a mask, to form a deep p-type implant (118a, 118b). N-type dopants are implanted into the silicon carbide substrate through the same opening in the mask, to form a shallow n-typc implant (124a, 124b) relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel (136a, 136b) may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivty, while the n-type dopant having low diffusivity remains relatively fixed. Thereby, a p-base may be formed around an n-type source. Lateral and vertical power MOSFETs may be fabricated.
摘要:
Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.
摘要:
PROBLEM TO BE SOLVED: To prevent voltage breakdown in an edge due to a high electric field, by implanting electric charge into a zone of a junction termination extension in a semiconductor device comprising a pn junction such that effective charge density decreases stepwise toward the edge.SOLUTION: An embodiment comprises a pn junction. Both a p-conducting layer 3 and an n-conducting layer 2 of the pn junction constitute doped silicon carbide layers. In an edge of a highly doped conducting layer of the pn junction, electric charge implantation is repeated such that the width of a mask 10 decreases stepwise toward the outermost edge, that is, total charge or effective surface charge density decreases stepwise from an initial value at the main pn junction to zero or almost zero at the outermost edge of the junction in a radial direction from the central part of the junction toward the outermost edge.
摘要:
A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1014 cm−3, and a concentration of transition metals impurities less than 5×1014 cm−3. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700° C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.