公开(公告)号：US09270292B2

公开(公告)日：2016-02-23

申请号：US14769945

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf Sundblad ,  Emil Hjalmarsson

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1255 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/126

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract translation: 用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器包括基于模数转换器操作的N个组成模数转换器的阵列 操作时钟以提供数字输出信号，N个采样保持单元连接到基于M个定时信号中的相应一个的相应组成模数转换器的输入，其中不使用定时信号 时钟两个或更多个采样和保持单元，一个或多个数字输出处理单元，其基于相应的一个提供组成模数转换器的数字输出的采样作为数字输出信号的采样 的M个定时信号，以及定时电路，其生成模数转换器操作时钟信号，每个定时信号具有M / R周期，其中M小于或等于N.

公开(公告)号：US09602123B2

公开(公告)日：2017-03-21

申请号：US15107568

申请日：2014-12-03

Applicant: Anacatum Design AB ,  Fingerprint Cards AB

Inventor： Rolf Sundblad ,  Staffan Holmbring ,  Robert Hägglund ,  Emil Hjalmarsson

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/10 ,  H03M1/38 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/1245 ,  H03M1/0624 ,  H03M1/1009 ,  H03M1/1265 ,  H03M1/38 ,  H03M1/46

Abstract: A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

公开(公告)号：US20160006447A1

公开(公告)日：2016-01-07

申请号：US14769914

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf SUNDBLAD

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1004 ,  H03M1/1057 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245

Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.

Abstract translation: 操作用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器的方法包括针对组成模数转换器阵列的至少一些激活的每一个 转换器，定义第一组和第二组组成模数转换器，将第一组的每个模数转换器的模拟输入馈送到不完整测量的参考值，并使每个模数转换器 第一组具有一个定时信号，将第二组的模拟 - 数字转换器的模拟输入馈送到模拟输入信号，以在数字输出端产生中间组成数字输出信号，并为每个模拟 - 具有定时信号之一的第二组的数模转换器，其中没有定时信号用于对第二组的模数转换器中的两个或更多个进行定时。

公开(公告)号：US09350374B2

公开(公告)日：2016-05-24

申请号：US14771835

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf Sundblad ,  Robert Hägglund ,  Staffan Holmbring

IPC: H03M1/00 ,  H03M1/12 ,  G02F7/00

CPC classification number: H03M1/1215 ,  G02F7/00 ,  H03M1/00 ,  H03M1/004 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/123

Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni, of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni≧1 and Σi=1L Ni≦N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni, constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

Abstract translation: 用于将L个模拟输入信号转换为L个相应的数字输出信号的时间交织的模拟 - 数字转换器包括N（N> L）个组成模数转换器的阵列，每个具有模拟输入和数字输出， 每个适于数字化模拟输入样本，以及适于（对于由i = 1,2，...，L索引的L个模拟输入信号中的每一个）的控制器，选择一个数量为Ni的组成模数转换器 从N个构成模数转换器（其中Ni≥1和＆Sgr; i = 1L Ni＆nlE; N）的阵列中，将模拟输入信号的每个采样数据化为所选择的Ni， 模数转换器。 模数转换器还包括适于（对于每个L个模拟输入信号）的多路复用多个所选择的Ni构成模数转换器中的每一个的数字化采样以产生数字输出信号的多路复用器。

公开(公告)号：US20160020777A1

公开(公告)日：2016-01-21

申请号：US14771835

申请日：2014-03-07

Applicant: ANACATUM DESIGN AB

Inventor： Rolf SUNDBLAD ,  Robert HÄGGLUND ,  Staffan HOLMBRING

IPC: H03M1/12

CPC classification number: H03M1/1215 ,  G02F7/00 ,  H03M1/00 ,  H03M1/004 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/123

Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni≧1 and Σi=1L Ni≦N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

Abstract translation: 用于将L个模拟输入信号转换为L个相应的数字输出信号的时间交织的模拟 - 数字转换器包括N（N> L）个组成模数转换器的阵列，每个具有模拟输入和数字输出， 每个适于数字化模拟输入采样，以及适于（对于由i = 1,2，...，L索引的L个模拟输入信号中的每一个）的控制器，从 N组成模数转换器（其中Ni≥1和＆Sgr; i = 1L Ni＆nlE; N）的阵列，并且使得模拟输入信号的每个采样在选定的Ni构成模数转换器中的相应一个中被数字化， 数字转换器。 模数转换器还包括适于（对于每个L个模拟输入信号）的多路复用多个所选择的Ni构成模数转换器中的每一个的数字化采样以产生数字输出信号的多路复用器。

公开(公告)号：US20150381195A1

公开(公告)日：2015-12-31

申请号：US14769945

申请日：2014-03-07

Applicant: ANACATUM DESIGN AB

Inventor： Rolf SUNDBLAD ,  Emil HJALMARSSON

IPC: H03M1/12

CPC classification number: H03M1/1255 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/126

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract translation: 用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器包括基于模数转换器操作的N个组成模数转换器的阵列 操作时钟以提供数字输出信号，N个采样保持单元连接到基于M个定时信号中的相应一个的相应组成模数转换器的输入，其中不使用定时信号 时钟两个或更多个采样和保持单元，一个或多个数字输出处理单元，其基于相应的一个提供组成模数转换器的数字输出的采样作为数字输出信号的采样 的M个定时信号，以及定时电路，其生成模数转换器操作时钟信号，每个定时信号具有M / R周期，其中M小于或等于N.

公开(公告)号：US20160322984A1

公开(公告)日：2016-11-03

申请号：US15107568

申请日：2014-12-03

Applicant: Anacatum Design AB ,  Fingerprint Cards AB

Inventor： Rolf SUNDBLAD ,  Staffan HOLMBRING ,  Robert HÄGGLUND ,  Emil HJALMARSSON

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/46 ,  H03M1/38

CPC classification number: H03M1/1245 ,  H03M1/0624 ,  H03M1/1009 ,  H03M1/1265 ,  H03M1/38 ,  H03M1/46

Abstract: A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal. The cognitive network is adapted to receive the digital converted signal of the analog-to-digital converter, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

Abstract translation: 公开了一种通过模拟信号输入端口连接到模拟信号源并适于产生基于经由模拟信号输入端口接收的模拟输入信号的数字输出信号的认知信号转换器。 认知信号转换器包括模数转换器和认知网络。 模拟 - 数字转换器适于基于模拟输入信号，采样时钟信号和处理时钟信号，通过根据采样时钟信号对模拟输入信号进行采样并量化每个模拟输入信号来产生数字转换信号 采样，其中量化处理由处理时钟信号操作。 认知网络适于接收模拟 - 数字转换器的数字转换信号，基于接收的数字转换信号和模拟信号的一个或多个特性来控制采样时钟信号和处理时钟信号中的至少一个 源，并且基于接收到的数字转换信号产生数字输出信号。 还公开了相应的集成电路，电子设备和方法。

公开(公告)号：US09331708B2

公开(公告)日：2016-05-03

申请号：US14769914

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf Sundblad

IPC: H03M1/36 ,  H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1004 ,  H03M1/1057 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245

Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.

Abstract translation: 操作用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器的方法包括针对组成模数转换器阵列的至少一些激活的每一个 转换器，定义第一组和第二组组成模数转换器，将第一组的每个模数转换器的模拟输入馈送到不完整测量的参考值，并使每个模数转换器 第一组具有一个定时信号，将第二组的模拟 - 数字转换器的模拟输入馈送到模拟输入信号，以在数字输出端产生中间组成数字输出信号，并为每个模拟 - 具有定时信号之一的第二组的数模转换器，其中没有定时信号用于对第二组的模数转换器中的两个或更多个进行定时。