Dynamically configurable interface cards with variable memory size
    7.
    发明授权
    Dynamically configurable interface cards with variable memory size 失效
    具有可变内存大小的动态配置接口卡

    公开(公告)号:US5448710A

    公开(公告)日:1995-09-05

    申请号:US661584

    申请日:1991-02-26

    CPC classification number: G06F12/0623

    Abstract: Circuitry facilitates configuration of a memory within an interface card. The configuration includes configuring the memory size and the memory address space. A register stores configuration information from the computer system. Control lines are connected to the register and distribute information from the register to locations on the interface card. A comparator produces an output which indicates whether an address on address lines from the computer system is addressing memory locations within the memory. The comparator does this by comparing address bits on a first set of the address lines with control bits on a first set of the control lines. Logical circuitry, connected between a subset of the first set of the address lines and the comparator, is used to mask, from the comparator, address bits on the subset of the first set of address lines. Additional logical circuitry, connected to the second set of the control lines and connected between the subset of the first set of address lines and the memory is used for masking, from the memory, the address bits on the subset of the first set of address lines. When the address bits on the subset of the first set of address lines are masked from the comparator, the address bits on the subset of the first set of address lines are not masked from the memory. When the address bits on the subset of the first set of address lines are masked from the memory, the address bits on the subset of the first set of address lines are not masked from the comparator.

    Abstract translation: 电路有助于配置接口卡内的存储器。 配置包括配置内存大小和内存地址空间。 寄存器存储来自计算机系统的配置信息。 控制线连接到寄存器,并将信息从寄存器分配到接口卡上的位置。 比较器产生一个输出,其指示来自计算机系统的地址线上的地址是否在寻址存储器内的存储器位置。 比较器通过将第一组地址线上的地址位与第一组控制线上的控制位进行比较来进行。 连接在第一组地址线的子集与比较器之间的逻辑电路用于从比较器屏蔽第一组地址线的子集上的地址位。 连接到第二组控制线并连接在第一组地址线的子集和存储器之间的附加逻辑电路用于从存储器屏蔽第一组地址线的子集上的地址位 。 当第一组地址线的子集上的地址位从比较器被屏蔽时,第一组地址线的子集上的地址位不被从存储器屏蔽。 当第一组地址线的子集上的地址位被从存储器屏蔽时,第一组地址线的子集上的地址位不被比较器屏蔽。

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