公开(公告)号：US6096604A

公开(公告)日：2000-08-01

申请号：US366739

申请日：1999-08-04

申请人： Cher Liang Cha ,  Anqing Zhang ,  Zhifeng Joseph Xie ,  Eng Fong Chor

发明人： Cher Liang Cha ,  Anqing Zhang ,  Zhifeng Joseph Xie ,  Eng Fong Chor

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336 ,  H01L21/8239 ,  H01L29/72

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11543

摘要： This invention relates to the new reversed flash memory device which has improved electrical performance, yield and reliability because of better control of the dielectric interfaces resulting from first making the poly 2 control gate within the silicon substrate. The reverse structure is novel, as are the described process methods for forming the reverse stacking order.Shallow trenched isolation (STI) is first formed in the p-silicon substrate and encompasses the poly 2 control gate region; then the interpoly dielectric is grown/deposited on that single crystal silicon substrate. The floating poly 1 is formed on top of this uniform interpoly dielectric that has well-controlled surface smoothness. The tunnel oxide layer is formed on the floating poly 1 layer, and the source/drain is implanted on a straddling additional poly layer. There are fewer edges and associated stress weaknesses in the dielectric breakdown of both the reversed interpoly dielectric and the floating tunnel oxide. The results are improved electrical quality and more acceptable electrical parameters, including reversed flash memory devices with gate length dimensions below 0.35 microns.

摘要翻译： 本发明涉及新的反向闪存器件，其具有改进的电性能，产量和可靠性，因为通过在硅衬底内首先制造聚二极管控制栅导致的电介质界面的更好控制。 反向结构是新颖的，以及用于形成反向堆叠顺序的所述方法。 首先在p硅衬底中形成浅沟槽隔离（STI）并且包围聚二极管控制区域; 然后在该单晶硅衬底上生长/沉积多晶硅电介质。 浮动聚1形成在该均匀的多晶硅电介质的顶部，其具有良好控制的表面平滑度。 隧道氧化物层形成在浮动聚1层上，并且源极/漏极注入到跨接的附加多晶硅层上。 在反向互聚电介质和浮动隧道氧化物的介电击穿中存在较少的边缘和相关的应力弱点。 结果是改善的电气质量和更可接受的电气参数，包括栅极长度尺寸小于0.35微米的反向闪存器件。

公开(公告)号：US6064201A

公开(公告)日：2000-05-16

申请号：US114125

申请日：1998-07-13

申请人： Cher Liang Randall Cha ,  Hao Gong ,  Eng Fong Chor ,  Lap Chan

发明人： Cher Liang Randall Cha ,  Hao Gong ,  Eng Fong Chor ,  Lap Chan

IPC分类号： G01R33/038 ,  G01N27/90 ,  G01R31/00 ,  G01R33/00 ,  G01R33/12 ,  G01V3/00

CPC分类号： G01Q60/54 ,  B82Y35/00 ,  G01Q60/56 ,  G01R33/0385 ,  B82Y25/00 ,  Y10S977/852 ,  Y10S977/879

摘要： Small metallic patches embedded in a mainly non-metallic surface may be detected and mapped by placing a wire coil at the free end of a cantilever, with a fine tip made of a ferro-magnetic material located at its center. An alternating current is passed through the coil so that when it is near a metallic patch eddy currents are induced in the patch. These produce a small magnetic moment in the patch which pulls the tip towards the surface. This movement of the tip is detected by observing a light beam that is reflected off the surface of the cantilever. By plotting the output of a photodetector, sensistive to small changes in the reflected beam's position, as a function of the tip's location over the surface, a map of the metallic patches is produced.

摘要翻译： 通过将线圈放置在悬臂的自由端，可以通过将位于其中心的铁磁性材料制成的细小尖端放置在主要非金属表面上的小金属贴片。 交流电流通过线圈，使得当其接近金属贴片时，在贴片中引起涡流。 这些在贴片中产生小的磁矩，将尖端朝向表面拉动。 通过观察从悬臂表面反射​​的光束来检测尖端的这种移动。 通过绘制光电检测器的输出，对反射光束位置的小变化敏感，作为尖端在表面上的位置的函数，产生了金属贴图。

公开(公告)号：US06252277B1

公开(公告)日：2001-06-26

申请号：US09392392

申请日：1999-09-09

申请人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

发明人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

IPC分类号： H01L2972

CPC分类号： H01L29/66621 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

摘要： Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

摘要翻译： 描述了形成具有嵌入在硅沟槽内的多晶硅栅电极的MOSFET。 MOSFET保留了具有光刻图案化多晶硅栅电极的常规MOSFET的所有特征，包括沿沟槽壁形成的鲁棒LDD（轻掺杂漏极）区域。 因为栅极电介质永远不会暴露于等离子体蚀刻或水性化学蚀刻，所以可以形成低于100埃的栅介质膜而没有缺陷。 在光刻图案化多晶硅栅电极的制造中遇到的过蚀刻和衬底尖峰的问题不会发生。 整个过程仅使用两个光刻步骤。 第一步骤通过图案化场隔离来定义硅有源面积，第二步限定在形成器件的有源区域内的沟槽。 新工艺使用相同的光刻步骤总数来形成MOSFET器件元件作为常规工艺，但对薄栅极氧化物的保护更为广泛。

公开(公告)号：US07400018B2

公开(公告)日：2008-07-15

申请号：US11462846

申请日：2006-08-07

申请人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

发明人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/6659

摘要： A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

摘要翻译： 实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。 提供体硅衬底。 在体硅衬底上沉积碳掺杂硅层。 生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。 通过以下步骤在起始晶片上制造集成电路器件。 在起始晶片上形成栅电极。 将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。 植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作 用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

公开(公告)号：US07109099B2

公开(公告)日：2006-09-19

申请号：US10688047

申请日：2003-10-17

申请人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

发明人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Jae Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

IPC分类号： H01L21/425 ,  H01L21/36 ,  H01L21/20 ,  H01L21/265

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/6659

摘要： A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

摘要翻译： 实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。 提供体硅衬底。 在体硅衬底上沉积碳掺杂硅层。 生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。 通过以下步骤在起始晶片上制造集成电路器件。 在起始晶片上形成栅电极。 将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。 植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作 用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

公开(公告)号：US20060270168A1

公开(公告)日：2006-11-30

申请号：US11462846

申请日：2006-08-07

申请人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

发明人： Chung Foong Tan ,  Jinping Liu ,  Hyeok Lee ,  Bangun Indajang ,  Eng Fong Chor ,  Shiang Yang Ong

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/6659

摘要： A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

摘要翻译： 实现了在光栅掺杂分布的间隙a-c硅界面处将碳结合到晶片中的方法。 提供体硅衬底。 在体硅衬底上沉积碳掺杂硅层。 生长外延硅层覆盖碳掺杂硅层以提供集成电路器件制造的起始晶片。 通过以下步骤在起始晶片上制造集成电路器件。 在起始晶片上形成栅电极。 将LDD和源极和漏极区域注入到与栅电极相邻的起始晶片中。 植入铟以形成与LDD区域相邻并且位于栅电极下方的卤素植入物，其中所述卤素注入延伸到外延硅层和碳掺杂硅层之间的界面，其中碳掺杂硅层中的碳离子用作 用于由光晕植入物形成的硅间隙的硅间隙槽，以防止范围二次缺陷形成的结束。

公开(公告)号：US07071069B2

公开(公告)日：2006-07-04

申请号：US10743247

申请日：2003-12-22

申请人： Chung Foong Tan ,  Hyeokjae Lee ,  Eng Fong Chor ,  Elgin Quek

发明人： Chung Foong Tan ,  Hyeokjae Lee ,  Eng Fong Chor ,  Elgin Quek

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656

摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.

摘要翻译： 口袋植入法减少缺陷。 我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。 我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。 接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。 非晶浅植入区域形成在无定形袋区域上方的第二深度处。 非晶浅植入区域之上的衬底优选保持结晶。 我们执行S / D植入程序以形成深S / D区域。 我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。