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    Recombinant cyclopentanone monooxygenase [cpmo]
    1.
    发明授权
    Recombinant cyclopentanone monooxygenase [cpmo] 失效
    重组环戊酮单加氧酶[cpmo]

    公开(公告)号：US07541168B2

    公开(公告)日：2009-06-02

    申请号：US11727730

    申请日：2007-03-28

    申请人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    发明人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    IPC分类号： C12N9/02 ,  C07H21/04

    CPC分类号： C12N9/0073 ,  C12Y114/13016

    摘要： Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mr, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

    摘要翻译： 来自Comamonas（以前为假单胞菌）的环戊酮1,2-单加氧酶（CPMO） 菌株NCIMB 9872进行降解途径的第二步，其允许细菌使用环戊醇作为生长的唯一碳源。 在本发明中，报道了CPMO编码基因（cpnB）在4.3kb SphI片段上的定位，确定其序列。 发现由该基因编码的550个氨基酸的CPMO多肽（Mr，62,111）与不动杆菌属的环己酮1,2-单加氧酶（CHMO）的序列具有36.5％的同一性。 菌株NCIMB 9871.62-kDa CPMO在大肠杆菌中表达为IPTG诱导蛋白。

    Semiconductor memory device with several access enabled using single port memory cell
    3.
    发明授权
    Semiconductor memory device with several access enabled using single port memory cell 有权
    具有多路访问功能的半导体存储器件使用单端口存储单元

    公开(公告)号：US6134154A

    公开(公告)日：2000-10-17

    申请号：US281215

    申请日：1999-03-30

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai

    IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C8/16 ,  G11C11/419

    摘要： In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a plurality of word lines and is connected to one of a plurality of bit lines such that a plurality of columns are formed from the plurality of memory cells. A word line selecting section selects one of the plurality of word lines based on a first address. A first column selector selects one of the plurality of columns as a first column based on the first address. A second column selector selects another one of the plurality of columns as a second column based on a second address. An address data of a predetermined portion of the first address is not equal to an address data of the second address. An input/output section includes a first sense amplifier and a first buffer. A first read operation is performed to a first memory cell connected to the selected word line and the first column through the first sense amplifier and the first column selector and a first write operation is performed to a second memory cell connected to the selected word line and the second column through the first buffer and the second column selector.

    摘要翻译： 在半导体存储器件中，多个存储单元被布置成矩阵。 多个存储单元中的每一个连接到多个字线中的一个，并且连接到多个位线中的一个，使得从多个存储单元形成多个列。 字线选择部分基于第一地址来选择多个字线之一。 第一列选择器基于第一地址选择多个列之一作为第一列。 第二列选择器基于第二地址选择多个列中的另一列作为第二列。 第一地址的预定部分的地址数据不等于第二地址的地址数据。 输入/输出部分包括第一读出放大器和第一缓冲器。 通过第一读出放大器和第一列选择器对连接到所选字线和第一列的第一存储单元执行第一读操作，并且对连接到所选字线的第二存储单元执行第一写操作，并且 第二列通过第一缓冲区和第二列选择器。

    Static type semiconductor memory device having a digit-line potential equalization circuit
    4.
    发明授权
    Static type semiconductor memory device having a digit-line potential equalization circuit 失效
    具有数字线电位均衡电路的静态型半导体存储器件

    公开(公告)号：US5841716A

    公开(公告)日：1998-11-24

    申请号：US934854

    申请日：1997-09-22

    申请人： Hiroaki Iwaki

    发明人： Hiroaki Iwaki

    IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： A semiconductor memory device includes precharging circuit for supplying a current to selected digit line pair and equalizing circuit for equalizing potential of complementary digit lines forming all of digit line pairs. Only digit line pair selected by a column address input signal is precharged by the precharging circuit. The potentials of the complementary digit lines forming all digit line pairs is equalized respectively by the equalizing circuit after precharging operation.

    摘要翻译： 半导体存储器件包括用于向选定的数字线对提供电流的预充电电路和用于均衡形成所有数字线对的互补数字线的电位的均衡电路。 只有通过列地址输入信号选择的数字线对被预充电电路预充电。 形成所有数字线对的互补数字线的电位分别由预充电操作后的均衡电路均衡。

    Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude
    5.
    发明授权
    Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude 失效
    具有锁存电路的锁存电路和半导体集成电路具有电压振幅较大的控制信号

    公开(公告)号：US06404254B2

    公开(公告)日：2002-06-11

    申请号：US09166585

    申请日：1998-10-06

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai ,  Susumu Kurosawa

    IPC分类号： H03K3286

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356173

    摘要： A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode, and in that MOSFETs applied with a control signal include a first conductivity type MOSFET having a high threshold and a second conductivity type MOSFET having a low threshold, a voltage amplitude of the control signal being larger than a power supply voltage. The semiconductor integrated circuit can be realized in that the high speed operation in the active mode and the low power consumption in the standby mode are compatible with each other, and it is sufficient if a power switch for the logic circuit is inserted at only either of the high level power supply voltage line side and the low level power supply voltage line side. In addition, the control signals are very few, and a fine timing control for changing over the mode is no longer required.

    摘要翻译： 一种半导体集成电路，其被配置为在备用模式中停止向逻辑电路供电，从而实现低功耗，包括锁存电路，其特征在于，作为控制信号，时钟信号在主动 模式，并且在备用模式下提供用于创建信息保持条件的信号，并且施加控制信号的MOSFET包括具有高阈值的第一导电型MOSFET和具有低阈值的第二导电类型MOSFET， 控制信号的幅度大于电源电压。 可以实现半导体集成电路，即主动模式中的高速操作和待机模式中的低功耗彼此兼容，并且如果用于逻辑电路的电源开关仅插入到 高电平电源电压侧和低电平电源电压线一侧。 此外，控制信号非常少，并且不再需要用于改变模式的精细定时控制。

    Latch type sense amplifier circuit
    6.
    发明授权
    Latch type sense amplifier circuit 有权
    锁存型读出放大器电路

    公开(公告)号：US06255862B1

    公开(公告)日：2001-07-03

    申请号：US09502231

    申请日：2000-02-11

    申请人： Kouichi Kumagai ,  Hiroaki Iwaki

    发明人： Kouichi Kumagai ,  Hiroaki Iwaki

    IPC分类号： H03F345

    CPC分类号： G11C7/065

    摘要： A latch type sense amplifier circuit comprises first and second latch circuits which output the same output signals when a potential difference between a bit line pair is equal to or greater than a predetermined value. The first and second latch circuits output different output signals when the potential difference between the bit line pair is less than the predetermined value. The latch type sense amplifier circuit further comprises a comparison result signal generating circuit which compares the output signals from the first and second latch circuits and outputs a signal indicative of the comparison result.

    摘要翻译： 锁存型读出放大器电路包括当位线对之间的电位差等于或大于预定值时输出相同输出信号的第一和第二锁存电路。 当位线对之间的电位差小于预定值时，第一和第二锁存电路输出不同的输出信号。 锁存型读出放大器电路还包括比较结果信号发生电路，其比较来自第一和第二锁存电路的输出信号，并输出指示比较结果的信号。

    Semiconductor integrated circuit having a sleep mode with low power and small area
    7.
    发明授权
    Semiconductor integrated circuit having a sleep mode with low power and small area 有权
    具有低功率和小面积的睡眠模式的半导体集成电路

    公开(公告)号：US06208170B1

    公开(公告)日：2001-03-27

    申请号：US09286029

    申请日：1999-04-05

    申请人： Hiroaki Iwaki ,  Kouichi Kumagai

    发明人： Hiroaki Iwaki ,  Kouichi Kumagai

    IPC分类号： H03K19094

    CPC分类号： G11C5/14

    摘要： A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

    摘要翻译： 半导体集成电路包括具有全局源极线VCC，源极开关晶体管耦合到VCC的局部源极线QVCC和全局接地线VSS，低阈值逻辑（组合）电路的电源电路，其连接在QVCC和 VSS和连接在VCC和VSS之间的数据存储（顺序）电路。 数据存储电路包括用于从逻辑电路接收数据的低阈值输入部分和用于锁存由输入部分接收的数据的高阈值锁存部分。 模式开关晶体管插入在低阈值逻辑电路和VSS之间，低阈值输入部分和VCC之间以及低阈值输入部分和VSS之间，用于实现半导体集成电路的睡眠模式。 降低电路规模可以保持低功耗。

    Cloning, sequencing and expression of a comamonas cyclopentanone 1,2-monooxygenase-encoding gene in Escherichia coli
    8.
    发明授权
    Cloning, sequencing and expression of a comamonas cyclopentanone 1,2-monooxygenase-encoding gene in Escherichia coli 失效
    在大肠杆菌中克隆，测序和表达环戊烯酮-1,2-单加氧酶基因

    公开(公告)号：US07214520B2

    公开(公告)日：2007-05-08

    申请号：US10312585

    申请日：2001-07-13

    申请人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    发明人： Hiroaki Iwaki ,  Yoshie Hasegawa ,  Peter C. K. Lau

    IPC分类号： C12N9/02 ,  C12N15/70 ,  C12N1/21 ,  C12N15/03 ,  C12Q1/68 ,  C12P21/06 ,  C07H21/04

    CPC分类号： C12N9/0073 ,  C12Y114/13016

    摘要： Cyclopentanone 1,2-monooxygenase (CPMO) from Comamonas (previously Pseudomonas) sp. strain NCIMB 9872 carries out the second step of a degradation pathway that allows the bacterium to use cyclopentanol as a sole carbon source for growth. In the present invention there is reported the localization of the CPMO-encoding gene (cpnB) on a 4.3-kb SphI fragment, the determination of its sequence. The 550-amino acid CPMO polypeptide (Mt, 62,111) encoded by the gene was found to have 36.5% identity with the sequence of cyclohexanone 1,2-monooxygenase (CHMO) of Acinetobacter sp. strain NCIMB 9871. The 62-kDa CPMO was expressed in E. coli as an IPTG-inducible protein.

    摘要翻译： 来自Comamonas（以前为假单胞菌）的环戊酮1,2-单加氧酶（CPMO） 菌株NCIMB 9872进行降解途径的第二步，其允许细菌使用环戊醇作为生长的唯一碳源。 在本发明中，报道了CPMO编码基因（cpnB）在4.3kb SphI片段上的定位，确定其序列。 发现由该基因编码的550个氨基酸的CPMO多肽（MATT，62,111）与不动杆菌属的环己酮1,2-单加氧酶（CHMO）的序列具有36.5％的同一性。 菌株NCIMB 9871.62-kDa CPMO在大肠杆菌中表达为IPTG诱导蛋白。

    Low dissipation inverter circuit
    9.
    发明授权
    Low dissipation inverter circuit 失效
    低功耗逆变电路

    公开(公告)号：US06100720A

    公开(公告)日：2000-08-08

    申请号：US287582

    申请日：1999-04-06

    申请人： Kouichi Kumagai ,  Hiroaki Iwaki

    发明人： Kouichi Kumagai ,  Hiroaki Iwaki

    IPC分类号： H03K17/693 ,  H03K5/151 ,  H03K19/00 ,  H03K19/0948

    CPC分类号： H03K19/0019 ,  H03K5/151

    摘要： An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

    摘要翻译： 逆变器电路具有用于接收互补输入信号的第一和第二输入端子，用于输出从互补输入信号产生的互补输出信号的第一和第二输出端子，以及一对整流器部分， 输出端子的电位侧到输出端子的较低电位，以节省功耗。

    Compact semiconductor device using SOI.cndot.CMOS technology
    10.
    发明授权
    Compact semiconductor device using SOI.cndot.CMOS technology 失效
    紧凑型半导体器件采用SOI.CMOS技术

    公开(公告)号：US6069373A

    公开(公告)日：2000-05-30

    申请号：US98864

    申请日：1998-06-17

    申请人： Hiroaki Iwaki

    发明人： Hiroaki Iwaki

    IPC分类号： H01L27/092 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L27/10

    CPC分类号： H01L27/0207 ,  H01L27/1203

    摘要： A square measure of a basic cell and a basic circuit cell of a semiconductor device used a SOI.cndot.CMOS technology is reduced. In the semiconductor device used a SOI.cndot.CMOS technology, the basic cells constituted by two pieces of PMOS and two pieces of NMOS are arranged in order of the PMOS, the PMOS, the NMOS and NMOS or NMOS, the NMOS, the PMOS and the PMOS in a row, and the diffused layer of a portion on which the PMOS and the NMOS adjoin are formed in a manner to adjoin directly. Moreover, the power source wiring and the grounding wiring are arranged around the basic cell in a manner to being held in common with the adjacent cells, and at least one of PMOS diffused layers is arranged so as to be able to be connected with a power source wiring through a contact directly and at least one of NMOS diffused layers is arranged so as to be able to be connected with a grounding wiring through a contact directly.

    摘要翻译： 使用SOI.CMOS技术的半导体器件的基本单元和基本电路单元的平方测量被减少。 在使用SOI.CMOS技术的半导体器件中，由PMOS和NMOS构成的基本单元按PMOS，PMOS，NMOS和NMOS或NMOS，NMOS，PMOS和PMOS的顺序排列 PMOS以及与PMOS和NMOS邻接的部分的扩散层以直接相邻的方式形成。 此外，电源布线和接地布线以与相邻单元共同的方式布置在基本单元周围，并且PMOS扩散层中的至少一个布置成能够与电源连接 直接通过触点的源极布线和NMOS扩散层中的至少一个布置成能够通过触点直接与接地布线连接。