公开(公告)号：US20140168002A1

公开(公告)日：2014-06-19

申请号：US14235027

申请日：2012-07-25

申请人： Hironori Sakamoto ,  Shigeyuki Niimura ,  Junji Yamagata ,  Keizo Nishida

发明人： Hironori Sakamoto ,  Shigeyuki Niimura ,  Junji Yamagata ,  Keizo Nishida

IPC分类号： G01S7/34

CPC分类号： G01S7/34

摘要： The object of the present invention is to provide a radar receiver that can steadily and reliably detect the target in the close zone without largely complicating the construction compared to the conventional radar apparatuses. The radar receiver according to the present invention comprises a receiving unit 15 that detects or modulates a received wave for detecting a target, the received wave arriving from the target in response to a transmitting wave transmitted towards the target, and a control unit 19 that sets a gain of the receiving unit 15 to a value at which the receiving unit is prevented from falling into a saturation region by a component of the transmission wave that wraps around the receiving unit 15 through an aerial system used for transmission of the transmission wave during a period in which the transmission wave is being transmitted.

摘要翻译： 本发明的目的是提供一种雷达接收机，其能够相对于常规的雷达装置而不会使构造更加复杂化，能够稳定可靠地检测近距离的目标。 根据本发明的雷达接收机包括：接收单元15，其检测或调制用于检测目标的接收波，响应于朝向目标发送的发送波，从目标到达的接收波;以及控制单元19，其设置 接收单元15的增益为接收单元通过在接收单元15中通过用于传输发送波的空中系统而包围在接收单元15周围的传输波的分量而被阻止接收单元的值 正在发送发送波的周期。

公开(公告)号：US20110246169A1

公开(公告)日：2011-10-06

申请号：US13075733

申请日：2011-03-30

申请人： Hironori SAKAMOTO

发明人： Hironori SAKAMOTO

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5036

摘要： A semiconductor circuit designing supporting system, includes: a storage unit in which two models of a first model and a second model are stored as device models a semiconductor device; and an operation unit. The operating unit includes: a characteristic variation calculating section configured to calculate a variation of a device characteristic when process parameters are varied by using the first model; and an analyzing section configured to normalize based on the variation, an error between a device characteristic calculated by using the second model and actual measurement data and to analyze the second model by using the normalized error.

摘要翻译： 一种半导体电路设计支持系统，包括：存储单元，其中第一模型和第二模型的两个模型作为半导体器件的器件模型存储; 和操作单元。 操作单元包括：特性变化计算部分，被配置为当通过使用第一模型来改变处理参数时，计算设备特性的变化; 以及分析部，被配置为基于所述变化进行归一化，通过使用所述第二模型计算的设备特性与实际测量数据之间的误差，并且通过使用所述归一化误差来分析所述第二模型。

公开(公告)号：US07671684B2

公开(公告)日：2010-03-02

申请号：US11994702

申请日：2005-07-05

申请人： Tamaki Honda ,  Hironori Sakamoto ,  Kenjiro Okadome

发明人： Tamaki Honda ,  Hironori Sakamoto ,  Kenjiro Okadome

IPC分类号： H03F3/04

CPC分类号： H03F1/301 ,  H03F3/193 ,  H03F2200/108 ,  H03F2200/18 ,  H03F2200/453

摘要： A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

摘要翻译： FET偏置电路施加不与FET放大电路的放大元件FET单独调整的偏置电压。 在FET偏置电路中，提供了具有连接到放大元件FETa的栅极的栅极和连接到放大元件FET a的源极的源极的监视元件FET m，并且具有相对于 基本上与放大元件FET a的漏极电流成比例的偏置电压。 在FET偏置电路中还设置有用于施加偏置电压的固定偏置电路，使得放大元件FETa通过向监视元件FET m施加偏置电压而进入预定的工作等级，使得流向监视元件的漏极电流 FET m进入预定的操作类。

公开(公告)号：US06539202B1

公开(公告)日：2003-03-25

申请号：US09448057

申请日：1999-11-23

申请人： Kazuo Yamashita ,  Hironori Sakamoto ,  Tomohiro Sanpei ,  Tamaki Honda ,  Hiroshi Morita

发明人： Kazuo Yamashita ,  Hironori Sakamoto ,  Tomohiro Sanpei ,  Tamaki Honda ,  Hiroshi Morita

IPC分类号： H04B1500

CPC分类号： H04B1/109

摘要： An interference canceling device comprising a flat phase IF narrow band BPF. A signal which has been branched from a signal on the main line is filtered by the BPF and is recombined with the signal on the main line. Phase rotation caused by frequency separation from the pass band center frequency does not occur because the phase characteristics of the BPF are substantially flat in the pass band. Thus, interference existing not only in a pin-point frequency, but over a band of frequencies can be cancelled.

摘要翻译： 一种包括平坦相IF窄带BPF的干扰消除装置。 从主线上的信号分支的信号被BPF滤波，并与主线上的信号重新组合。 由于BPF的相位特性在通带中基本平坦，所以不会发生由通带中心频率的频率分离引起的相位旋转。 因此，不仅存在针脚频率，而且在频带上存在的干扰可以被消除。

公开(公告)号：US06479874B2

公开(公告)日：2002-11-12

申请号：US09161510

申请日：1998-09-28

申请人： Kenji Hibino ,  Masao Kunitou ,  Kazuyuki Yamasaki ,  Tetsuji Togami ,  Hironori Sakamoto ,  Kiyokazu Hashimoto

发明人： Kenji Hibino ,  Masao Kunitou ,  Kazuyuki Yamasaki ,  Tetsuji Togami ,  Hironori Sakamoto ,  Kiyokazu Hashimoto

IPC分类号： H01L2976

CPC分类号： H01L27/112 ,  G11C11/5692 ,  H01L27/11253

摘要： A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

摘要翻译： 一种半导体ROM器件，其能够获得可以安全地区分存储在存储单元中的数据的参考电流，所述多级屏蔽ROM用于存储每个存储单元的三级或更多级的多级数据。 该装置包括存储单元，其中相应于注入到单元晶体管的沟道区域的离子的量设置阈值电压，并存储三个或多个电平的多电平数据，用于产生用于比较的参考电流的参考单元 从存储器单元读出电流，以及与参考单元相邻设置的虚拟单元。 在参考单元的沟道区域和虚拟单元的沟道区域中，同时注入离子以在参考单元和虚拟单元中建立相等的阈值电压。

公开(公告)号：US5363072A

公开(公告)日：1994-11-08

申请号：US965171

申请日：1992-10-23

申请人： Hironori Sakamoto ,  Akira Ito ,  Toshio Nojima

发明人： Hironori Sakamoto ,  Akira Ito ,  Toshio Nojima

IPC分类号： H01P5/02 ,  H01P5/12 ,  H03F3/60 ,  H03F3/68 ,  H03H7/48

CPC分类号： H01P5/02 ,  H03F3/602

摘要： In a power amplifying apparatus which has a high-frequency power divider and combiner and two to four parallel-operated power amplifiers, in which a change is made in the number of the parallel-operated power amplifiers so as to adjust output power, there are provided a power dividing circuit D.sub.1 having a transmission line Wd.sub.51 serving as an impedance transformer set in such a manner that the power loss is minimized by assigning an intermediate number 3 between 2 and 4 both of which indicate the number of divisions, and having four output terminals, and a power combining circuit S.sub.1 having a transmission line Ws.sub.51 serving as an impedance transformer set in such a manner that the power loss is minimized by assigning the intermediate number 3 indicative of the number of combinations, and having four input terminals.

摘要翻译： 在具有高频功率分配器和组合器的功率放大装置和两到四个并联操作的功率放大器中，其中并行操作的功率放大器的数量改变以便调节输出功率， 提供了一种功率分配电路D1，其具有用作阻抗变换器的传输线Wd51，以使得功率损耗最小化的方式，通过分配两个表示分割数的2和4之间的中间数3，并且具有四个输出 端子，以及具有用作阻抗变换器的传输线Ws51的功率组合电路S1，以通过分配表示组合数的中间数3并具有四个输入端的方式使功率损耗最小化。

公开(公告)号：US5313657A

公开(公告)日：1994-05-17

申请号：US964669

申请日：1992-10-22

申请人： Hironori Sakamoto ,  Satoru Ohara ,  Toshio Nojima ,  Shoichi Narahashi ,  Makoto Maeta

发明人： Hironori Sakamoto ,  Satoru Ohara ,  Toshio Nojima ,  Shoichi Narahashi ,  Makoto Maeta

IPC分类号： H04B1/76 ,  H04B17/00 ,  H04B17/20 ,  H04B17/29 ,  H04B1/10 ,  H03F3/66 ,  G01R19/00

CPC分类号： H04B1/76 ,  H04B17/29

摘要： In a receiver comprising a receiver filter (12) with a frequency attenuation band and a pilot oscillator (25) for generating a pilot oscillation signal with a pilot frequency in the frequency attenuation band, a coupler (26) couples the pilot oscillation signal and a filtered receiver signal of the receiver filter to form a coupled signal. A low noise amplifier (13) amplifies the coupled signal into an amplified signal which comprises an amplified receiver signal component derived from the filtered receiver signal and an amplified pilot oscillation signal component derived from the pilot oscillation signal. A branching filter (27) branches the amplified signal into the amplified receiver signal component and the amplified pilot oscillation signal. A pilot signal component detector unit (28) detects the amplified pilot oscillation signal component to produce a direct pilot signal. A failure monitoring unit (29) monitors the direct pilot signal to produce a fault signal when the direct pilot signal is found faulty.

摘要翻译： 在包括具有频率衰减频带的接收机滤波器（12）和用于在频率衰减频带中产生具有导频的导频振荡信号的导频振荡器（25）的接收机中，耦合器（26）将导频振荡信号和 滤波的接收机滤波器的接收器信号以形成耦合信号。 低噪声放大器（13）将耦合信号放大为放大信号，该放大信号包括从经滤波的接收机信号导出的放大的接收机信号分量和从导频振荡信号导出的放大的导频振荡信号分量。 分路滤波器（27）将放大的信号分支为放大的接收机信号分量和放大的导频振荡信号。 导频信号分量检测器单元（28）检测放大的导频振荡信号分量以产生直接导频信号。 当发现直接导频信号有故障时，故障监视单元（29）监视直接导频信号以产生故障信号。

公开(公告)号：US07222060B2

公开(公告)日：2007-05-22

申请号：US10668974

申请日：2003-09-24

申请人： Takashi Shimizu ,  Hironori Sakamoto

发明人： Takashi Shimizu ,  Hironori Sakamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

摘要翻译： 根据从MOS晶体管的晶体管模型的参数和具有各种扩散长度的晶体管的参数提取的扩散长度相关参数的数据，扩散长度相关参数校正单元产生扩散长度依赖性的近似表达式 这些参数，并通过使用创建的近似表达式计算要使用的参数校正值而不是原始参数值。 因此，可以容易地使用校正值而不是原始参数值，由此可以容易地创建具有不同扩散长度DL的MOS晶体管的晶体管模型。 考虑到MOS晶体管的漏极电流的扩散长度依赖性的电路仿真可以进行，从而可以实现高精度的仿真。

公开(公告)号：US06489844B2

公开(公告)日：2002-12-03

申请号：US09735759

申请日：2000-12-13

申请人： Kazuo Yamashita ,  Akira Ito ,  Hironori Sakamoto ,  Keijiro Ito ,  Akira Yamada ,  Norihisa Kawasumi

发明人： Kazuo Yamashita ,  Akira Ito ,  Hironori Sakamoto ,  Keijiro Ito ,  Akira Yamada ,  Norihisa Kawasumi

IPC分类号： H03F366

CPC分类号： H03F1/3235

摘要： A feed-forward amplifier and a controller thereof. Two types of second pilot signals, sum frequency and difference frequency of a base pilot signal and a local oscillation signal, are generated by an injection-side mixer and injected into a distortion detection loop. Part of a signal appearing at an output terminal is branched, converted in frequency by a detection-side mixer using the local oscillation signal, filtered by a narrow-band filter, input to a synchronizing detector with the filtered output of the filter as error signals, and synchronizing detected with reference to the base pilot signal so as to generate control signals for a distortion rejection loop. The spectrums of the second pilot signals may be spread. A process to cancel the input signal component at the detection side may be performed. A simple circuit configuration enhances the distortion component rejection and suppression effect and shortens the time required until an optimum control state is established.

摘要翻译： 一种前馈放大器及其控制器。 通过注入侧混频器产生两种类型的第二导频信号，基频导频信号和本地振荡信号的和频和差频，并将其注入到失真检测环路中。 出现在输出端子处的信号的一部分通过检测侧混频器被分频，使用本地振荡信号进行滤波，由窄带滤波器滤波，输入到同步检测器，滤波器的滤波器作为误差信号 并且参考基准导频信号进行同步检测，以产生用于失真抑制环路的控制信号。 可以扩展第二导频信号的频谱。 可以执行消除检测侧的输入信号分量的处理。 简单的电路配置增强了失真分量抑制和抑制效果，缩短了所需的时间，直到建立最佳控制状态。

公开(公告)号：US06486724B2

公开(公告)日：2002-11-26

申请号：US09773354

申请日：2001-01-31

申请人： Hironori Sakamoto ,  Tamaki Honda ,  Taketo Takahashi

发明人： Hironori Sakamoto ,  Tamaki Honda ,  Taketo Takahashi

IPC分类号： H03K17687

CPC分类号： H03F1/306 ,  H03F2200/447 ,  H03F2200/75

摘要： A circuit for biasing an FET, comparing a gate bias voltage of the FET with a reference voltage at an operational amplifier and performing closed-loop control on the gate bias voltage of the FET with the output of the operational amplifier. The temperature characteristics of the mutual conductance of the FET is compensated by setting the temperature characteristics of one or both of two voltage dividing resistors. Variations in a drain bias current due to input signal level and temperature changes can be suppressed. The circuit at the gate and the circuit at the drain are separate, making possible class A, class AB, and class B operations. The voltage drop at the gate resistor can be ignored so that the gate resistor can be designed with priority given to stability of the RF characteristics.

摘要翻译： 用于偏置FET的电路，将FET的栅极偏置电压与运算放大器的参考电压进行比较，并且利用运算放大器的输出对FET的栅极偏置电压执行闭环控制。 通过设置两个分压电阻中的一个或两个的温度特性来补偿FET的互导的温度特性。 可以抑制由输入信号电平和温度变化引起的漏极偏置电流的变化。 栅极电路和漏极电路分开，使A类，AB类和B类工作成为可能。 可以忽略栅极电阻器处的电压降，从而可以根据RF特性的稳定性优先设计栅极电阻器。