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    Method of forming a semiconductor device
    3.
    发明授权
    Method of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US07309628B2

    公开(公告)日：2007-12-18

    申请号：US10989937

    申请日：2004-11-15

    申请人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Cary Gunn, III

    发明人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Cary Gunn, III

    IPC分类号： H01L21/8238

    CPC分类号： H01L23/48 ,  G02B6/132 ,  H01L21/84 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.

    摘要翻译： 半导体器件形成为集成电路的一部分。 形成在有源半导体层中的半导体器件被保护器包围，该保护器提供抵抗污染物的扩散阻挡层，并且还提供辅助以避免在化学机械抛光期间半导体器件上方的凹陷。 蚀刻在半导体器件上方和保护器内部的电介质，以形成接收光纤，电磁信号源或电磁信号负载之一的开口。 剩余的电介质是厚度基本均匀的层。 监护人建立在正常集成电路过程的一部分。 这些包括接触层，通孔层和互连层。

    Method of forming a semiconductor device
    4.
    发明申请
    Method of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US20060105563A1

    公开(公告)日：2006-05-18

    申请号：US10989937

    申请日：2004-11-15

    申请人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Gunn

    发明人： Omar Zia ,  Hsiao-Hui Chen ,  Lawrence Gunn

    IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L21/00

    CPC分类号： H01L23/48 ,  G02B6/132 ,  H01L21/84 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.

    摘要翻译： 半导体器件形成为集成电路的一部分。 形成在有源半导体层中的半导体器件被保护器包围，该保护器提供抵抗污染物的扩散阻挡层，并且还提供辅助以避免在化学机械抛光期间半导体器件上方的凹陷。 蚀刻在半导体器件上方和保护器内部的电介质，以形成接收光纤，电磁信号源或电磁信号负载之一的开口。 剩余的电介质是厚度基本均匀的层。 监护人建立在正常集成电路过程的一部分。 这些包括接触层，通孔层和互连层。

    Extendable method for revising patterned microelectronic conductor layer layouts
    5.
    发明授权
    Extendable method for revising patterned microelectronic conductor layer layouts 有权
    用于修改图案化微电子导体层布局的可扩展方法

    公开(公告)号：US06862722B2

    公开(公告)日：2005-03-01

    申请号：US10325387

    申请日：2002-12-20

    申请人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

    发明人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for revising a patterned conductor layer and a system for revising the patterned conductor layer employ an unoccupied equivalent wiring location. The unoccupied equivalent wiring location is provided in each of a series of wiring layout records. At least one optional wiring pattern may be formed in the unoccupied equivalent wiring location. The method and system provide for extending to all of the series of wiring layout records an optional wiring pattern and an interconnect option formed within a single one of the series of wiring layout records.

    摘要翻译： 修改图案化导体层的方法和用于修改图案化导体层的系统采用空闲的等效布线位置。 在一系列接线布局记录中提供空闲的等效接线位置。 至少一个可选的布线图案可以形成在空闲的等效布线位置。 该方法和系统提供延伸到所有一系列布线布局记录中的可选布线图案和互连选项，其形成在一系列布线布局记录中。

    PHOTRONIC DEVICE WITH REFLECTOR AND METHOD FOR FORMING
    6.
    发明申请
    PHOTRONIC DEVICE WITH REFLECTOR AND METHOD FOR FORMING 审中-公开
    具有反射器和形成方法的PHOTRONIC装置

    公开(公告)号：US20130313668A1

    公开(公告)日：2013-11-28

    申请号：US13479668

    申请日：2012-05-24

    申请人： Gregory S. Spencer ,  John R. Alvis ,  Hsiao-Hui Chen ,  Joseph F. Orcutt ,  Srivatsa G. Kundalgurki

    发明人： Gregory S. Spencer ,  John R. Alvis ,  Hsiao-Hui Chen ,  Joseph F. Orcutt ,  Srivatsa G. Kundalgurki

    IPC分类号： H01L27/144 ,  H01L31/18

    CPC分类号： G02B6/43 ,  H01L31/02325

    摘要： A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.

    摘要翻译： 光电设备包括具有通过基板的开口的基板。 所述光电设备还包括在所述基板上方的包括在所述开口上方的绝缘层。 光电设备还包括绝缘层上的有源层。 光电设备还包括形成在有源层中的光活性器件，其中光活性器件在开口之上。 光电设备还包括形成在有源层中的有源电子电路。 光电设备还包括在开口中的绝缘层上的反射层。

    Desensitizing static random access memory (SRAM) to process variations
    7.
    发明授权
    Desensitizing static random access memory (SRAM) to process variations 有权
    使静态随机存取存储器（SRAM）脱敏来处理变化

    公开(公告)号：US08116119B1

    公开(公告)日：2012-02-14

    申请号：US12758579

    申请日：2010-04-12

    申请人： Tao Peng ,  Hsiao Hui Chen

    发明人： Tao Peng ,  Hsiao Hui Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C7/08 ,  G11C7/14 ,  G11C8/16 ,  G11C11/413 ,  Y10S257/903

    摘要： A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a write replica circuit generating a signal when data has been written to the write replica circuit. A wordline of the memory array is turned off responsive to the signal. The write replica circuit can include an additional column comprising at least one dual port dummy memory cell, and write detection circuitry coupled to the dual port dummy memory cell detecting when data has been written to the dual port dummy memory cell and responsively generating the signal. The signal generated by the write detection circuitry indicates a successful write operation to the dual port dummy memory cell.

    摘要翻译： 静态随机存取存储器（SRAM）可以包括形成存储器阵列的多个列，其中每列包括耦合到位线和字线的多个存储单元，以及当数据被写入写入时产生信号的写复制电路 复制电路。 根据信号，存储器阵列的字线被关闭。 写复制电路可以包括包括至少一个双端口虚拟存储器单元的附加列，以及耦合到双端口虚拟存储器单元的写入检测电路，当数据被写入双端口虚拟存储器单元并且响应地生成信号时，该检测电路被检测。 由写检测电路产生的信号指示对双端口伪存储器单元的成功写操作。

    Extendable method for revising patterned microelectronic conductor layer layouts
    8.
    发明申请
    Extendable method for revising patterned microelectronic conductor layer layouts 审中-公开
    用于修改图案化微电子导体层布局的可扩展方法

    公开(公告)号：US20050132315A1

    公开(公告)日：2005-06-16

    申请号：US11044750

    申请日：2005-01-26

    申请人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

    发明人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5077

    摘要： Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring location within which may be formed at least one optional wiring pattern. When there is designed within an unoccupied equivalent wiring location for a single wiring layout record within the series of wiring layout records at least one optional wiring pattern and an interconnect option to the at least one optional wiring pattern.

    摘要翻译： 在修改图案化导体层的方法和用于修改图案化导体层的系统中，在针对一系列微电子制造的布线布局数据库内的一系列布线布局记录内的每个布线布局记录内提供未占用的等效布线 其中的位置可以形成至少一个可选的布线图案。 当在一系列布线布局内的单个布线布局记录的未占用的等效布线位置内设计有至少一个可选布线图案和至少一个可选布线图案的互连选项时。

    Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities
    9.
    发明授权
    Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities 有权
    具有字节程序，字节擦除和字节读取功能的非易失性半导体存储器阵列

    公开(公告)号：US06888754B2

    公开(公告)日：2005-05-03

    申请号：US10355997

    申请日：2003-01-31

    申请人： Yue-Der Chih ,  Shu-Chen Chang ,  Hsiao-Hui Chen

    发明人： Yue-Der Chih ,  Shu-Chen Chang ,  Hsiao-Hui Chen

    IPC分类号： G11C8/00 ,  G11C16/06 ,  G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/0425

    摘要： This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

    摘要翻译： 本发明提供一种具有字节擦除能力的存储器阵列及其外围电路。 本发明的优点是能够访问用于程序，擦除和读取操作的字节。 本发明允许通过添加一个字线开关和一个源线开关来访问用于编程，擦除和读取操作的每个字节的访问。 此外，本发明利用新的偏压条件来减小高压装置上的电压应力。 此外，本发明使用用于本地字线驱动器电路和本地源极线驱动器电路的单独的专用电源。 这与主存储器阵列分割成8列的子阵列相结合。 这允许将高电压放置在所选的8列（字节）子阵列上。 这也大大降低了存储器单元的电压应力并提高了长期的可靠性。