公开(公告)号：US20090256540A1

公开(公告)日：2009-10-15

申请号：US12420324

申请日：2009-04-08

Applicant: Ta-Yung Yang ,  Jenn-Yu Lin

Inventor： Ta-Yung Yang ,  Jenn-Yu Lin

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: A low drop-out regulator according to the present invention comprises an unregulated DC input terminal receiving an input voltage. A pass circuit is coupled between the unregulated DC input terminal and a regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to an output voltage or/and an output current.

Abstract translation: 根据本发明的低压差调节器包括接收输入电压的未调节的DC输入端子。 通过电路耦合在未调节的DC输入端子和用于向调节的DC输出端子供电的稳压DC输出端子之间。 放大电路控制通过电路，以响应于输出电压或/和输出电流提供恒定电压或/和恒定电流。

公开(公告)号：US20080290410A1

公开(公告)日：2008-11-27

申请号：US11913044

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract translation: 提供了具有隔离结构的MOSFET。 N型MOSFET包括设置在P型衬底中的第一N型掩埋层和P型外延层。 P型FET包括第二N型掩埋层和设置在P型衬底中的P型外延层。 第一N型掩埋层和P型外延层提供FET之间的隔离。 此外，设置在P型外延层中的多个分离的P型区域进一步提供隔离效果。 在第一厚电场氧化物层和第一P型区域之间存在用于提高N型FET的击穿电压的第一间隙。 在第二厚场氧化物层和第二N阱之间存在第二间隙，用于提高P型FET的击穿电压。

公开(公告)号：US20070117328A1

公开(公告)日：2007-05-24

申请号：US11622429

申请日：2007-01-11

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095

Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.

Abstract translation: 提供具有场区域的垂直晶体管的结构。 垂直晶体管包括通过调制场区域的掺杂密度，长度和几何图案，并且通过将场区域连接到边缘芯的相应阱，形成在靠近垂直晶体管的芯区域的衬底中的场掺杂区域 垂直晶体管的区域，本发明实现了场区域的短长度的稳定的击穿电压。 因此，可以减少设备面积和制造成本。

公开(公告)号：US20070001229A1

公开(公告)日：2007-01-04

申请号：US11174018

申请日：2005-07-01

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L29/87

Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

Abstract translation: 静电放电（ESD）器件具有寄生SCR结构和可控触发电压。 通过调制轻掺杂阱的边缘和位于轻掺杂阱的两端的重掺杂区的边缘之间的距离来实现ESD器件的可控触发电压。 由于距离和触发电压是线性比例的，因此可以将触发电压设置为从最小值到最大值的特定值。

公开(公告)号：US20060030107A1

公开(公告)日：2006-02-09

申请号：US10914943

申请日：2004-08-09

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US20050184338A1

公开(公告)日：2005-08-25

申请号：US10786703

申请日：2004-02-24

Applicant: Chih-Feng Huang ,  Ta-Yung Yang ,  Jenn-Yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-Yung Yang ,  Jenn-Yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/735 ,  H01L29/739 ,  H01L29/772 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Abstract translation: 根据本发明的高电压LDMOS晶体管包括在N阱的扩展漏极区域中的P场和分割的P场。 P场和分割的P场在N阱中形成结场，其中漂移区在击穿之前被完全耗尽。 因此，实现更高的击穿电压，并且允许N阱的较高的掺杂密度。 较高的掺杂密度可以有效降低LDMOS晶体管的导通电阻。 此外，在源极扩散区域之下产生的N阱为源极区域提供了低阻抗路径，其限制了漏极区域和源极区域之间的晶体管电流。

公开(公告)号：US20050007083A1

公开(公告)日：2005-01-13

申请号：US10617515

申请日：2003-07-10

Applicant: Ta-yung Yang ,  Yi-Hsin Leu ,  Chern-Lin Chen ,  Jenn-Yu Lin

Inventor： Ta-yung Yang ,  Yi-Hsin Leu ,  Chern-Lin Chen ,  Jenn-Yu Lin

IPC: G05F1/40 ,  G05F1/56 ,  H02M1/00 ,  H02M1/42 ,  H02M7/00

CPC classification number: H02M1/4225 ,  H02M2001/4275 ,  Y02B70/126

Abstract: A regulated power supply having power factor correction control includes a multi-vector error amplifier. The multi-vector error amplifier provides an error signal that is used to regulate a switching mechanism of the power supply. The multi-vector error amplifier acts to provide a low distortion error signal during steady-state operation, while responding rapidly and smoothly to sudden load changes.

公开(公告)号：US08710813B2

公开(公告)日：2014-04-29

申请号：US12420324

申请日：2009-04-08

Applicant: Ta-Yung Yang ,  Jenn-Yu Lin

Inventor： Ta-Yung Yang ,  Jenn-Yu Lin

IPC: G05F1/565 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: A low drop-out regulator is disclosed. An unregulated DC input terminal receives an input voltage. A pass circuit is coupled between the unregulated DC input terminal and a regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to an output voltage or/and an output current.

Abstract translation: 公开了一种低压差调节器。 未调节的直流输入端子接收输入电压。 通过电路耦合在未调节的DC输入端子和用于向调节的DC输出端子供电的稳压DC输出端子之间。 放大电路控制通过电路，以响应于输出电压或/和输出电流提供恒定电压或/和恒定电流。

公开(公告)号：US07923787B2

公开(公告)日：2011-04-12

申请号：US11913044

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-Yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-Yung Yang

IPC: H01L21/70

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract translation: 提供了具有隔离结构的MOSFET。 N型MOSFET包括设置在P型衬底中的第一N型掩埋层和P型外延层。 P型FET包括第二N型掩埋层和设置在P型衬底中的P型外延层。 第一N型掩埋层和P型外延层提供FET之间的隔离。 此外，设置在P型外延层中的多个分离的P型区域进一步提供隔离效果。 在第一厚电场氧化物层和第一P型区域之间存在用于提高N型FET的击穿电压的第一间隙。 在第二厚场氧化物层和第二N阱之间存在第二间隙，用于提高P型FET的击穿电压。

公开(公告)号：US20090050962A1

公开(公告)日：2009-02-26

申请号：US11913037

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.

Abstract translation: 提供了具有用于单片集成的隔离结构的MOSFET器件。 P型MOSFET包括设置在P型衬底中的第一N阱，设置在第一N阱中的第一P型区，设置在第一P型区中的P +漏极区，第一源电极 形成有P +源极区域和N +接触区域。 第一个N阱围绕着P +源极区域和N +接触区域。 N型MOSFET包括设置在P型衬底中的第二N阱，设置在第二N阱中的第二P型区，设置在第二N阱中的N +漏极区，第二源电极 形成有N +源区和P +接触区。 第二P型区围绕N +源极区域和P +接触区域。 多个分离的P型区域设置在P型衬底中以提供晶体管的隔离。