公开(公告)号：US06373328B1

公开(公告)日：2002-04-16

申请号：US09759817

申请日：2001-01-10

申请人： Karl Rapp

发明人： Karl Rapp

IPC分类号： G05F110

摘要： A charge pump system includes a charge pumping circuit for outputting a high voltage VPP at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage VPP while minimizing power-supply current drain.

公开(公告)号：US5424997A

公开(公告)日：1995-06-13

申请号：US213902

申请日：1994-03-15

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： In order to permit the selection of aspect ratio for a given memory size, a semiconductor array utilizes switches to segment bit line columns, where each segment is associated with a specific set of memory locations and their respective data latches. After all of the data latches are loaded, the switches segment the bit line columns to allow simultaneous programming of those memory locations cells associated with each set of data latches. This sequence is repeated until all desired data storage cells are programmed.

摘要翻译： 为了允许选择给定存储器大小的宽高比​​，半导体阵列利用开关来分割位线列，其中每个段与特定的一组存储器位置及其相应的数据锁存器相关联。 在所有数据锁存器加载之后，开关对位线列进行分段，以允许与每组数据锁存器相关联的那些存储单元单元的同时编程。 重复该顺序，直到对所有期望的数据存储单元进行编程。

公开(公告)号：US5398001A

公开(公告)日：1995-03-14

申请号：US70614

申请日：1993-06-02

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： H03K5/151 ,  H03K3/04 ,  H03K5/13

CPC分类号： H03K5/151

摘要： A four phase clock generator, which can be employed to operate a charge pump, is configured using coupling elements that ensure that the four phases are non-overlapping. Two of the phases are created with delay buffers that have substantial delays that mainly determine the clock frequency. The delay buffers and coupling elements produce delays that are made variable in response to a control current. This provides a clock whose frequency is proportional to a control current.

摘要翻译： 可用于操作电荷泵的四相时钟发生器使用确保四相不重叠的耦合元件构成。 其中两个阶段由具有主要决定时钟频率的实质性延迟的延迟缓冲器创建。 延迟缓冲器和耦合元件产生响应于控制电流变化的延迟。 这提供了一个频率与控制电流成比例的时钟。

公开(公告)号：US4656374A

公开(公告)日：1987-04-07

申请号：US745094

申请日：1985-06-17

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： H03K3/011 ,  H03K3/013 ,  H03K3/356 ,  H03K3/286 ,  H03K3/353 ,  H03K17/04 ,  H03K17/687

CPC分类号： H03K3/356113 ,  H03K3/011 ,  H03K3/013

摘要： A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above about 1.2 volts for TTL compatibility. A single reference potential generator will provide a potential for a plurality of buffers so that its dissipation is low and is shared among the buffers. The result is a low power buffer circuit that is compensated for variations in supply voltage, temperature and device parameters.

摘要翻译： 公开了具有提供TTL逻辑响应的参考电位的CMOS缓冲器。 电路被配置为基本上绘制零电流。 参考电位发生器产生一个电位，该电位是高于约1.2伏的TTL通道的一个N沟道晶体管阈值。 单个参考电位发生器将为多个缓冲器提供电位，使得其耗散低并且在缓冲器之间共享。 结果是一个低功耗缓冲电路，补偿电源电压，温度和器件参数的变化。

公开(公告)号：US4464591A

公开(公告)日：1984-08-07

申请号：US391255

申请日：1982-06-23

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： H03K5/02 ,  H03K5/24 ,  G01R19/165 ,  G11C7/06

CPC分类号： H03K5/2472 ,  H03K5/023

摘要： A differential current sense amplifier is shown suitable for high speed semiconductor memory sensing. A reference current generation circuit is also developed for operating a plurality of sense amplifiers.

摘要翻译： 示出了适用于高速半导体存储器感测的差分电流读出放大器。 还开发了用于操作多个读出放大器的参考电流产生电路。

公开(公告)号：US4448167A

公开(公告)日：1984-05-15

申请号：US403197

申请日：1982-07-29

申请人： Werner Schmid ,  Karl Rapp

发明人： Werner Schmid ,  Karl Rapp

IPC分类号： F02M59/26 ,  F02M63/02 ,  F02M39/00

CPC分类号： F02M63/02 ,  F02M59/265

摘要： A fuel injection pump, embodied as a series pump, has a governor rod for rotating a pump piston provided with an oblique control groove. The pump piston further has at least one longitudinal groove, by means of which upon congruence with a fill and relief opening of the pump work chamber, a zero fuel supply can be established. With electrically controlled actuation of the governor rod, the appropriate adjustment of the end stops of the governor rod or the appropriate embodiment of the pump piston assures that the opening comes into congruence with a longitudinal groove adjoining the full-load working zone of the pump piston before the end stop of the governor rod is reached.

摘要翻译： 具有串联泵的燃料喷射泵具有调节杆，用于旋转设置有倾斜控制槽的泵活塞。 泵活塞还具有至少一个纵向凹槽，通过该凹槽与泵工作室的填充和释放开口一致，可以建立零燃料供应。 通过调节杆的电控致动，调节杆的端部挡块或泵活塞的适当实施例的适当调节确保了开口与邻近泵活塞的满负荷工作区的纵向槽相一致 在达到调速杆的终点之前。

公开(公告)号：US06813209B2

公开(公告)日：2004-11-02

申请号：US10685371

申请日：2003-10-14

申请人： Ethan A. Crain ,  Karl Rapp ,  Etan Shacham

发明人： Ethan A. Crain ,  Karl Rapp ,  Etan Shacham

IPC分类号： G11C702

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C2207/063

摘要： A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

摘要翻译： 公开了一种非常适合低频RFID系统的低读电流，低功耗读出放大器。 MOS晶体管从存储单元（通常为EEPROM）接收读取电流，电流镜由并联MOS晶体管形成。 电容器上的电荷通过复位脉冲清零后，镜电流集成在电容上。 定义一个时间段，在该时间段期间将电容器上的电压与第二电压进行比较。 第二电压由参考电压或虚设单元形成，在任一种情况下，参考电压约为存储在存储单元中的一个和零之间的逻辑边界。 具有或不具有输入滞后的比较器接收电容器上的电压和第二电压，并且在该时间段内，比较器的输出状态指示存储器单元的二进制内容。

公开(公告)号：US06639840B1

公开(公告)日：2003-10-28

申请号：US10037790

申请日：2002-01-03

申请人： A. Karl Rapp ,  Hungyu H. Hou

发明人： A. Karl Rapp ,  Hungyu H. Hou

IPC分类号： G11C1134

CPC分类号： G11C16/10

摘要： A non-volatile latch circuit that has minimal control circuitry is disclosed. The non-volatile latch circuit is typically used in applications where only several bits of data need to be stored in non-volatile memory. The non-volatile latch circuit can be programmed and read using three control signals: a programming voltage/supply voltage signal, a data in signal, and a read/{overscore (write)} signal. By using fewer control signals, the number of transistors used to implement the control circuitry within the non-volatile latch circuit is reduced and thus the non-volatile latch circuit consumes less chip area/volume on an integrated circuit device.

摘要翻译： 公开了一种具有最小控制电路的非易失性锁存电路。 非易失性锁存电路通常用于仅需要将数位数据存储在非易失性存储器中的应用中。 非易失性锁存电路可以使用三个控制信号进行编程和读取：编程电压/电源电压信号，信号中的数据，以及读/（超核（写信号）。通过使用更少的控制信号，使用的晶体管数量 实现非易失性锁存电路内的控制电路被减少，从而非易失性锁存电路在集成电路器件上消耗较少的芯片面积/体积。

公开(公告)号：US06351175B1

公开(公告)日：2002-02-26

申请号：US09662367

申请日：2000-09-13

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： H03K1776

CPC分类号： H03K19/1732

摘要： In accordance with the present invention a mode select circuit includes a bias circuit and a voltage level encoder. The mode select circuit further includes a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The bias circuit is coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the mode select terminal is not coupled to any of the configuration elements. The voltage level encoder is coupled to the mode select terminal for providing one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.

摘要翻译： 根据本发明，模式选择电路包括偏置电路和电压电平编码器。 模式选择电路还包括能够选择性地耦合到多个配置元件中的一个或多个的模式选择端子，以将模式选择端子偏置为多个预定电压中的一个。 当模式选择端子未耦合到任何配置元件时，偏置电路耦合到模式选择端子，用于将端子偏置为预定电压之一。 电压电平编码器耦合到模式选择端子，用于响应于模式选择端子被偏置到多个预定电压中的对应的一个，在多个电压电平编码器输出端子上提供多个电压电平代码中的一个。

公开(公告)号：US6150805A

公开(公告)日：2000-11-21

申请号：US186918

申请日：1998-11-06

申请人： A. Karl Rapp

发明人： A. Karl Rapp

IPC分类号： H01L27/04 ,  G05F3/26 ,  H01L21/822 ,  H02J1/00

CPC分类号： G05F3/262 ,  Y10S323/901

摘要： A method and circuits for generating a start-up signal to force a bistable reference circuit into a conducting state. The start-up signal ensures that the reference circuit operates to provide a desired output signal when power is applied. The start-up signal is self-generated and self-canceled, rather than relying on an externally supplied pulse, and is input to the reference circuit via a hysteresis circuit (e.g., Schmitt inverter).

摘要翻译： 一种用于产生启动信号以迫使双稳参考电路进入导通状态的方法和电路。 启动信号确保参考电路工作，以便在施加电源时提供所需的输出信号。 启动信号是自发生的并自取消，而不是依靠外部提供的脉冲，并通过滞后电路（例如施密特反相器）输入到参考电路。