公开(公告)号：US08994252B2

公开(公告)日：2015-03-31

申请号：US13540196

申请日：2012-07-02

申请人： Kentaro Nakanishi

发明人： Kentaro Nakanishi

IPC分类号： H01L41/09 ,  H03H9/10 ,  H03H9/19

CPC分类号： H03H9/1021 ,  H03H9/19

摘要： An AT-cut quartz plate having chamfered ridge portions and an almost rectangular shape in planar view, wherein a resonance frequency is equal to or larger than 7 MHz and equal to or smaller than 9 MHz, lengths of long and short sides of the rectangular shape are equal to or larger than 1.5 mm and equal to or smaller than 2.4 mm, and equal to or larger than a frequency difference between primary vibration and sub-vibration is equal to or larger than 975 kHz and equal to or smaller than 1,015 kHz.

摘要翻译： 在平面图中具有倒角脊部和大致矩形形状的AT切割石英板，其中共振频率等于或大于7MHz且等于或小于9MHz，矩形长边和短边的长度 等于或大于1.5mm且等于或小于2.4mm，并且等于或大于主振动和次振动之间的频率差等于或大于975kHz且等于或小于1,015kHz。

公开(公告)号：US20130009521A1

公开(公告)日：2013-01-10

申请号：US13540196

申请日：2012-07-02

申请人： Kentaro NAKANISHI

发明人： Kentaro NAKANISHI

IPC分类号： H01L41/047 ,  H01L41/04

CPC分类号： H03H9/1021 ,  H03H9/19

摘要： An AT-cut quartz plate having chamfered ridge portions and an almost rectangular shape in planar view, wherein a resonance frequency is equal to or larger than 7 MHz and equal to or smaller than 9 MHz, lengths of long and short sides of the rectangular shape are equal to or larger than 1.5 mm and equal to or smaller than 2.4 mm, and equal to or larger than a frequency difference between primary vibration and sub-vibration is equal to or larger than 975 kHz and equal to or smaller than 1,015 kHz.

摘要翻译： 在平面图中具有倒角脊部和大致矩形形状的AT切割石英板，其中共振频率等于或大于7MHz且等于或小于9MHz，矩形长边和短边的长度 等于或大于1.5mm且等于或小于2.4mm，并且等于或大于主振动和次振动之间的频率差等于或大于975kHz且等于或小于1,015kHz。

公开(公告)号：US20090020822A1

公开(公告)日：2009-01-22

申请号：US12164635

申请日：2008-06-30

申请人： Kentaro NAKANISHI ,  Hiromasa FUJIMOTO ,  Takayuki YAMADA

发明人： Kentaro NAKANISHI ,  Hiromasa FUJIMOTO ,  Takayuki YAMADA

IPC分类号： H01L27/118 ,  H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

摘要翻译： 半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。 第二侧壁具有比第一侧壁更小的厚度。

公开(公告)号：US08279610B2

公开(公告)日：2012-10-02

申请号：US12674505

申请日：2008-08-21

申请人： Minoru Iizuka ,  Koichi Kishimoto ,  Kozo Shibutani ,  Kentaro Nakanishi

发明人： Minoru Iizuka ,  Koichi Kishimoto ,  Kozo Shibutani ,  Kentaro Nakanishi

IPC分类号： H05K1/00 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L23/053 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16195 ,  H03H9/1021 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00

摘要： An electronic component package has a base in the shape of a rectangle as viewed from the top, and a metal lid. A terminal electrode on a base bottom surface and a circuit substrate are joined using a conductive adhesive material. In the electronic component package, a first terminal electrode group including two or more terminal electrodes formed in parallel is formed eccentrically to one corner position of the base bottom surface, and a single second terminal electrode, or a second terminal electrode group including two or more terminal electrodes formed in parallel, is formed eccentrically only to a first diagonal position diagonally opposite the one corner position. Also, no-electrode regions in which no terminal electrode is formed along a short side of the base are provided at another corner position facing the one corner position in a short side direction of the base, and a second diagonal position diagonally opposite the other corner position. At least one of the terminal electrodes is a ground terminal electrode connected to the metal lid.

摘要翻译： 电子部件封装具有从顶部观察为矩形形状的基部和金属盖。 使用导电性粘合剂材料将基底面上的端子电极和电路基板接合。 在电子部件封装中，包括形成为平行的两个以上的端子电极的第一端子电极组偏心地形成在底部底面的一个拐角位置，单个第二端子电极或包括两个以上的第二端子电极组 形成为平行的端子电极偏心地形成为与一个角位置对角地相对的第一对角线位置。 此外，在基座的短边方向上的与一个角位置相对的另一个角位置处设置有沿着基座的短边没有形成端子电极的无电极区域，并且与另一个角部对角地相对的第二对角线位置 位置。 至少一个端子电极是连接到金属盖的接地端子电极。

公开(公告)号：US07932141B2

公开(公告)日：2011-04-26

申请号：US12164635

申请日：2008-06-30

申请人： Kentaro Nakanishi ,  Hiromasa Fujimoto ,  Takayuki Yamada

发明人： Kentaro Nakanishi ,  Hiromasa Fujimoto ,  Takayuki Yamada

IPC分类号： H01L21/3205

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

摘要翻译： 半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。 第二侧壁具有比第一侧壁更小的厚度。

公开(公告)号：US06884643B2

公开(公告)日：2005-04-26

申请号：US10370079

申请日：2003-02-21

申请人： Kentaro Nakanishi ,  Hiroaki Nakaoka

发明人： Kentaro Nakanishi ,  Hiroaki Nakaoka

IPC分类号： G01R31/26 ,  H01L21/336 ,  H01L21/66 ,  H01L23/544 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L22/34 ,  H01L29/6656 ,  H01L29/7836

摘要： Semiconductor devices each having a semiconductor layer (1), a gate insulating film (2), a gate electrode (3), an offset spacer layer (4), and SD extension diffusion layers (6) into which ions have been implanted by using the gate electrode (3) and the offset spacer layer (4) as a mask are formed by varying the film thickness of the offset spacer layer (4) and leakage current values in the respective semiconductor devices are measured. The results of the measurements show that the film thickness value of the offset spacer layer (4) and the leakage current value have a correlation therebetween and that the film thickness value of the offset spacer layer (4) when the leakage current value becomes zero corresponds to the length of the portion of the semiconductor layer (1) extending from under the outer end of the offset spacer layer (4) to the tip end of an impurity diffusion layer.

摘要翻译： 每个半导体器件具有半导体层（1），栅极绝缘膜（2），栅电极（3），偏移间隔层（4）和SD延伸扩散层（6），通过使用 通过改变偏移间隔层（4）的膜厚度来形成作为掩模的栅电极（3）和偏移间隔层（4），并且测量各个半导体器件中的漏电流值。 测量结果表明，偏移间隔层（4）的膜厚值和漏电流值之间具有相关性，并且当漏电流值变为零时偏移间隔层（4）的膜厚值对应于 相对于从偏移间隔层（4）的外端延伸到杂质扩散层的末端的半导体层（1）的部分的长度。

公开(公告)号：US20090032878A1

公开(公告)日：2009-02-05

申请号：US11976668

申请日：2007-10-26

申请人： Kentaro Nakanishi ,  Takayuki Yamada

发明人： Kentaro Nakanishi ,  Takayuki Yamada

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L21/26513 ,  H01L21/823418 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device comprises a first gate electrode formed on a first region of a semiconductor substrate, a first impurity layer formed at least below both ends of the first gate electrode in the first region, a first side wall formed on both side surfaces of the first gate electrode, and a second impurity layer formed on both sides of the first side wall as viewed from the first gate electrode in the first region. The first impurity layer includes a first-conductivity type first impurity and a first-conductivity type second impurity having a larger mass number than that of the first impurity.

摘要翻译： 半导体器件包括形成在半导体衬底的第一区域上的第一栅极电极，在第一区域中至少在第一栅电极的两端形成的第一杂质层，形成在第一栅极电极的第一区域的两侧表面上的第一侧壁 栅极电极和形成在第一侧壁的两侧上的第二杂质层，在第一区域中从第一栅电极观察。 第一杂质层包括第一导电型第一杂质和质量数大于第一杂质的第一导电型第二杂质。

公开(公告)号：US08178929B2

公开(公告)日：2012-05-15

申请号：US13052546

申请日：2011-03-21

申请人： Kentaro Nakanishi ,  Hiromasa Fujimoto ,  Takayuki Yamada

发明人： Kentaro Nakanishi ,  Hiromasa Fujimoto ,  Takayuki Yamada

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

摘要翻译： 半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。 第二侧壁具有比第一侧壁更小的厚度。

公开(公告)号：US20110114353A1

公开(公告)日：2011-05-19

申请号：US12674505

申请日：2008-08-21

申请人： Minoru Iizuka ,  Koichi Kishimoto ,  Kozo Shibutani ,  Kentaro Nakanishi

发明人： Minoru Iizuka ,  Koichi Kishimoto ,  Kozo Shibutani ,  Kentaro Nakanishi

IPC分类号： H05K5/06 ,  H05K1/11 ,  H05K1/03

CPC分类号： H01L23/49838 ,  H01L23/053 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16195 ,  H03H9/1021 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00

摘要： An electronic component package has a base in the shape of a rectangle as viewed from the top, and a metal lid. A terminal electrode on a base bottom surface and a circuit substrate are joined using a conductive adhesive material. In the electronic component package, a first terminal electrode group including two or more terminal electrodes formed in parallel is formed eccentrically to one corner position of the base bottom surface, and a single second terminal electrode, or a second terminal electrode group including two or more terminal electrodes formed in parallel, is formed eccentrically only to a first diagonal position diagonally opposite the one corner position. Also, no-electrode regions in which no terminal electrode is formed along a short side of the base are provided at another corner position facing the one corner position in a short side direction of the base, and a second diagonal position diagonally opposite the other corner position. At least one of the terminal electrodes is a ground terminal electrode connected to the metal lid.

摘要翻译： 电子部件封装具有从顶部观察为矩形形状的基部和金属盖。 使用导电性粘合剂材料将基底面上的端子电极和电路基板接合。 在电子部件封装中，包括形成为平行的两个以上的端子电极的第一端子电极组偏心地形成在底部底面的一个拐角位置，单个第二端子电极或包括两个以上的第二端子电极组 形成为平行的端子电极偏心地形成为与一个角位置对角地相对的第一对角线位置。 此外，在基部的短边方向上的与一个角位置相对的另一个角位置设置有沿着基部的短边没有形成端子电极的无电极区域，并且与另一个角部对角地相对的第二对角线位置 位置。 至少一个端子电极是连接到金属盖的接地端子电极。

公开(公告)号：US07495295B2

公开(公告)日：2009-02-24

申请号：US11258931

申请日：2005-10-27

申请人： Kentaro Nakanishi ,  Isao Miyanaga ,  Atsuhiro Kajiya

发明人： Kentaro Nakanishi ,  Isao Miyanaga ,  Atsuhiro Kajiya

IPC分类号： H01L29/72

CPC分类号： H01L21/823462 ,  H01L21/823456

摘要： In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr3 satisfy Vdd1

摘要翻译： 在根据本发明的半导体器件中，核心晶体管Tr1的电源电压Vdd1，I / O晶体管Tr2的电源电压Vdd2和I / O晶体管Tr3的电源电压Vdd3满足Vdd1 < Vdd2