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    Semiconductor device and method of manufacturing the same
    3.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20050093089A1

    公开(公告)日：2005-05-05

    申请号：US10995283

    申请日：2004-11-24

    申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

    发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

    CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

    摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

    Method for extending electrically conductive layer into electrically insulating layer
    5.
    发明授权
    Method for extending electrically conductive layer into electrically insulating layer 失效
    将导电层延伸到电绝缘层中的方法

    公开(公告)号：US5418187A

    公开(公告)日：1995-05-23

    申请号：US202880

    申请日：1994-02-28

    申请人： Isao Miyanaga ,  Yasushi Okuda

    发明人： Isao Miyanaga ,  Yasushi Okuda

    IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/441

    CPC分类号： H01L21/76882

    摘要： A method of manufacturing semiconductor devices, which realizes miniaturization, a higher aspect ratio of a via hole, a higher yield and reliability, and a high degree of controllability, by completely filling the via hole by performing heat treatment on an electrically conductive thin film in a vacuum atmosphere. The method involves extending an electrically conductive layer into an electrically insulating layer arranged on the electrically conductive layer including the steps of forming an electrically conductive film on a side wall of a via hole extending in the electrically insulating layer from the electrically conductive layer toward the outside of the electrically insulating layer, and heating the electrically conductive film and the electrically conductive layer so that the electrically conductive film flows into the via hole and the electrically conductive layer projects into the via hole.

    摘要翻译： 通过对导电薄膜进行热处理，通过完全填充通孔，制造实现小型化，通孔的高宽比，高产率和可靠性以及高可控性的半导体器件的制造方法 真空气氛。 该方法包括将导电层延伸到布置在导电层上的电绝缘层中，包括以下步骤：在电绝缘层中从导电层向外延伸的通孔的侧壁上形成导电膜 的电绝缘层，并且加热导电膜和导电层，使得导电膜流入通孔，并且导电层突出到通孔中。

    Semiconductor device and method for fabricating the same
    6.
    发明申请
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20070131984A1

    公开(公告)日：2007-06-14

    申请号：US11522996

    申请日：2006-09-19

    申请人： Masayuki Kamei ,  Isao Miyanaga ,  Takayuki Yamada

    发明人： Masayuki Kamei ,  Isao Miyanaga ,  Takayuki Yamada

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823425 ,  H01L21/823418 ,  H01L21/823443

    摘要： A semiconductor device includes a first MIS transistor of a non-salicide structure and a second MIS transistor of a salicide structure which are both formed on a substrate of silicon. The first MIS transistor includes a first gate electrode of silicon, first sidewalls, a first source and drain, and plasma reaction films grown in a plasma atmosphere to cover the top surfaces of the first gate electrode and first source and drain.

    摘要翻译： 半导体器件包括非硅化物结构的第一MIS晶体管和硅化物结构的第二MIS晶体管，二者都形成在硅衬底上。 第一MIS晶体管包括硅的第一栅电极，第一侧壁，第一源极和漏极以及在等离子体气氛中生长以覆盖第一栅电极的顶表面和第一源极和漏极的等离子体反应膜。

    Method of forming insulating film and method of fabricating semiconductor device
    7.
    发明授权
    Method of forming insulating film and method of fabricating semiconductor device 失效
    形成绝缘膜的方法和制造半导体器件的方法

    公开(公告)号：US06800512B1

    公开(公告)日：2004-10-05

    申请号：US09662004

    申请日：2000-09-14

    申请人： Kazuichiro Itonaga ,  Akihiro Yamamoto ,  Hiroaki Nakaoka ,  Isao Miyanaga ,  Yoshinao Harada

    发明人： Kazuichiro Itonaga ,  Akihiro Yamamoto ,  Hiroaki Nakaoka ,  Isao Miyanaga ,  Yoshinao Harada

    IPC分类号： H01L2100

    CPC分类号： H01L21/31654 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/28247 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857

    摘要： With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

    摘要翻译： 通过在室内保持包括氧的气氛，并且将晶片保持在低温下，在室内产生的等离子体朝向晶片偏置，并且晶片经受等离子体。 暴露在晶片上的半导体层被氧化成氧化膜。 因此，即使在室温下也可以形成与热氧化不同的氧化膜。 该氧化适用于在清洁光致抗蚀剂膜时蚀刻的注入保护绝缘膜的恢复，多晶硅膜之间形成的台阶的松弛，沟槽内形成的台阶的松弛等。 此外，在去除用于形成包括金属的栅电极的光致抗蚀剂膜之前，可以通过保持光致抗蚀剂膜的这种氧化来形成污染保护膜。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5825193A

    公开(公告)日：1998-10-20

    申请号：US575735

    申请日：1995-12-18

    申请人： Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

    发明人： Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

    IPC分类号： G01R31/28 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G01R31/2884 ,  G01R31/2849

    摘要： A semiconductor integrated circuit apparatus having a plurality of semiconductor integrated circuit devices, each of the plurality of semiconductor devices including a semiconductor integrated circuit formed on a semiconductor substrate, a reference voltage input terminal formed on the semiconductor substrate which is operative for receiving a reference voltage input from outside of the semiconductor substrate, and a burn-in voltage control circuit formed on the semiconductor substrate operative for receiving the reference voltage which is output from the reference voltage input terminal. The burn-in voltage control circuit generates a burn-in supply voltage which is input to the semiconductor integrated circuit, and also maintains the burn-in supply voltage at the reference voltage level such that each of the integrated circuits receives a burn-in supply voltage having the same voltage level.

    摘要翻译： 一种具有多个半导体集成电路器件的半导体集成电路器件，所述多个半导体器件中的每一个包括形成在半导体衬底上的半导体集成电路，形成在所述半导体衬底上的参考电压输入端子，所述参考电压输入端子用于接收参考电压 从半导体衬底的外部输入，以及形成在半导体衬底上的老化电压控制电路，用于接收从参考电压输入端子输出的参考电压。 老化电压控制电路产生输入到半导体集成电路的老化电源电压，并且将老化电源电压维持在参考电压电平，使得每个集成电路接收老化电源 电压具有相同的电压电平。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06974987B2

    公开(公告)日：2005-12-13

    申请号：US10477924

    申请日：2003-02-14

    申请人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

    发明人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

    摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

    摘要翻译： 存储单元晶体管和沟槽电容器设置在存储区域中，CMOS的两个晶体管都设置在逻辑电路区域中。 提供了位线接触件31和在层间电介质30上延伸的位线32。 在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖，使得在源极扩散层18上不形成硅化物层。 提供板触点31以通过层间电介质30并将屏蔽线33连接到平板电极16b。 屏蔽线33布置在与位线32相同的互连层中。