公开(公告)号：US09070709B2

公开(公告)日：2015-06-30

申请号：US14119395

申请日：2011-06-09

Applicant: Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

Inventor： Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/265

CPC classification number: H01L29/66477 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract translation: 基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。 半导体材料层和栅极图案被覆盖层覆盖。 第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。 覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

公开(公告)号：US08735259B2

公开(公告)日：2014-05-27

申请号：US13555356

申请日：2012-07-23

Applicant: Yannick Le Tiec ,  Laurent Grenouillet ,  Maud Vinet

Inventor： Yannick Le Tiec ,  Laurent Grenouillet ,  Maud Vinet

IPC: H01L21/76

CPC classification number: H01L21/76 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76237 ,  H01L21/76283

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract translation: 一种在包括由半导体支撑层形成的绝缘体上半导体基板的基板和搁置在所述绝缘层上的绝缘层和置于所述绝缘层上的半导电层的器件中制造一个或多个沟槽的方法，所述方法包括以下步骤： ：a）通过位于精细半导体层上的掩模层中的开口局部掺杂所述绝缘层的给定部分，b）选择性地去除所述开口底部的所述给定掺杂区域。

公开(公告)号：US08722499B2

公开(公告)日：2014-05-13

申请号：US13357061

申请日：2012-01-24

Applicant: Maud Vinet ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme

Inventor： Maud Vinet ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme

IPC: H01L21/336

CPC classification number: H01L29/78603 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78648

Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.

Abstract translation: 场效应器件形成在具有通过电绝缘层与半导体膜分离的支撑衬底的绝缘体半导体衬底上。 源极和漏极形成在栅电极的每一侧的半导体膜中。 电绝缘层包括在半导体膜和支撑衬底之间具有面向栅电极的第一电容值的第一区域。 电绝缘层包括具有比半导体膜和支撑衬底面对源电极和漏电极的第一值更高的电容值的第二和第三区域。

公开(公告)号：US20140087524A1

公开(公告)日：2014-03-27

申请号：US14119395

申请日：2011-06-09

Applicant: Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

Inventor： Nicolas Posseme ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract translation: 基板依次包括支撑基板，电绝缘层，半导体材料层和栅极图案。 半导体材料层和栅极图案被覆盖层覆盖。 第一掺杂杂质通过覆盖层注入到半导体材料层中，以将第一掺杂杂质的最大浓度的厚度置于第一层中。 覆盖层被部分地消除，以形成离开源极/漏电极的横向间隔物。

公开(公告)号：US20120256262A1

公开(公告)日：2012-10-11

申请号：US13439356

申请日：2012-04-04

Applicant: Maud VINET ,  Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME

IPC: H01L29/772 ,  H01L21/768

CPC classification number: H01L29/78648 ,  H01L21/743 ,  H01L21/76283

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract translation: 场效应晶体管包括依次包括导电支撑衬底，电绝缘层和半导体材料层的衬底。 对置电极形成在支撑基板的面向半导体材料层的第一部分中。 绝缘图案围绕半导体材料层以描绘第一有源区域并且其部分地穿透到支撑层中以描绘第一部分。 导电接触通过绝缘图案从与对电极接触的第一侧表面穿过第二表面。 触点电连接到对电极。

公开(公告)号：US08232168B2

公开(公告)日：2012-07-31

申请号：US12521311

申请日：2007-12-28

Applicant: Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

Inventor： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

IPC: H01L21/336

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

Abstract: A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

Abstract translation: 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少 第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离 并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖， 硬掩模的临界尺寸大于第二块的临界尺寸。

公开(公告)号：US08115503B2

公开(公告)日：2012-02-14

申请号：US12123758

申请日：2008-05-20

Applicant: Maud Vinet

Inventor： Maud Vinet

IPC: G01R27/08 ,  G01R31/26

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  Y10T29/49004 ,  H01L2924/00

Abstract: A device for measuring the resistivity ρc of an interface between a semiconductor and a metal, including at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, and at least two interface portions containing the metal or an alloy of said semiconductor and said metal, wherein each of two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.

Abstract translation: 一种用于测量半导体和金属之间的界面的电阻率的装置，包括至少一个电介质层，至少一个基本矩形形状的基于半导体的元件，其布置在电介质层上，具有 纵向L和宽度方向W表面与电介质层接触并具有厚度t，以及至少两个界面部分，其包含所述半导体和所述金属的金属或合金，其中半导体元件的两个相对面中的每一个具有 表面等于t×W并垂直于与介电层接触的面，被其中一个界面部分完全覆盖。

公开(公告)号：US20110147849A1

公开(公告)日：2011-06-23

申请号：US12868488

申请日：2010-08-25

Applicant: Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

Inventor： Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

IPC: H01L27/088 ,  H01L21/98

CPC classification number: H01L27/1104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11

Abstract: An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.

Abstract translation: 一种集成电路，包括：第一晶体管; 第二晶体管，布置在第一晶体管上，沟道区形成在包括两个近似平行的主面的半导体层中; 导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且其中第二晶体管的沟道区域的部分包括在导电材料部分的部分中，并且第二晶体管的沟道区域被布置在导电材料的部分和栅极之间 第二晶体管。

公开(公告)号：US07812410B2

公开(公告)日：2010-10-12

申请号：US12168417

申请日：2008-07-07

Applicant: Michael Collonge ,  Maud Vinet ,  Olivier Thomas

Inventor： Michael Collonge ,  Maud Vinet ,  Olivier Thomas

IPC: H01L27/20 ,  H01L41/04 ,  H01L41/083

CPC classification number: G11C23/00 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/515 ,  H01L29/78654

Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

Abstract translation: 一种微电子器件，包括至少一个晶体管，其包括：在衬底上，具有覆盖有栅极介电区的沟道区的半导体区，悬浮在栅极介电区上方的移动栅极，并与栅极介电区隔开空位 栅极位于与栅极介电区域可调节的距离处，以及压电致动装置，其包括由至少一层静电在第一偏置电极上的压电材料形成的叠层，以及沉积在压电材料上的第二偏置电极 层，其中所述栅极附接到所述第一偏置电极并且与所述第一偏置电极接触，并且所述压电致动装置被配置为相对于所述沟道区移动所述栅极。

公开(公告)号：US20090294861A1

公开(公告)日：2009-12-03

申请号：US12466733

申请日：2009-05-15

Applicant: Olivier THOMAS ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

Inventor： Olivier THOMAS ,  Perrine Batude ,  Arnaud Pouydebasque ,  Maud Vinet

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

Abstract: A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises:a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line,a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level,the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.

Abstract translation: 一种非易失性随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平处，其中至少一个第一存取晶体管和至少一个第二存取晶体管 ，其分别布置在第一位线和第一存储节点之间，以及第二位线和第二存储节点之间，第一存取晶体管和第二存取晶体管具有连接到字线的栅极，第二多个 形成触发器并且位于所述堆叠的至少另一个层级下面的所述给定电平以下的所述第二多个晶体管的晶体管分别包括与所述第一多个晶体管的沟道区相对的栅电极 的晶体管，并且通过提供用于使得所述栅极电极和所述沟道区域耦合的绝缘区域与该沟道区域分离。