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    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS
    3.
    发明申请
    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 有权
    用于在有源区域部分地形成隔离斜面的微电子器件制造方法

    公开(公告)号：US20150294903A1

    公开(公告)日：2015-10-15

    申请号：US14425891

    申请日：2012-09-05

    申请人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    发明人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    IPC分类号： H01L21/762 ,  H01L21/306 ,  H01L21/265 ,  H01L21/84

    CPC分类号： H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

    摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

    摘要翻译： 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

    Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
    4.
    发明授权
    Method for fabricating microelectronic devices with isolation trenches partially formed under active regions 有权
    用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法

    公开(公告)号：US09437474B2

    公开(公告)日：2016-09-06

    申请号：US14425891

    申请日：2012-09-05

    申请人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    发明人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306

    CPC分类号： H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

    摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

    摘要翻译： 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

    Dual shallow trench isolation liner for preventing electrical shorts
    5.
    发明授权
    Dual shallow trench isolation liner for preventing electrical shorts 有权
    双浅沟槽隔离衬垫，用于防止电气短路

    公开(公告)号：US08703550B2

    公开(公告)日：2014-04-22

    申请号：US13525642

    申请日：2012-06-18

    申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

    摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

    摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

    DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS
    8.
    发明申请
    DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS 有权
    用于防止电气短路的双层防爆隔离衬套

    公开(公告)号：US20130334651A1

    公开(公告)日：2013-12-19

    申请号：US13525642

    申请日：2012-06-18

    申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

    摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

    摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

    SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS
    10.
    发明申请
    SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS 有权
    通过循环选择性外延沉积工艺沉积重金属半导体层

    公开(公告)号：US20140024203A1

    公开(公告)日：2014-01-23

    申请号：US13988436

    申请日：2010-11-19

    申请人： Vincent Destefanis ,  Nicolas Loubet

    发明人： Vincent Destefanis ,  Nicolas Loubet

    IPC分类号： H01L21/02

    CPC分类号： H01L21/0226 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02642

    摘要： The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

    摘要翻译： 沉积方法包括提供具有由半导体材料制成的第一单晶区和由绝缘材料制成的第二区的衬底。 在钝化步骤期间，钝化气氛被施加在衬底上，以便用掺杂杂质覆盖第一区域。 在沉积步骤期间，引入气态硅和/或锗前体并形成掺杂半导体膜。 半导体膜在第一区域上是单晶的，并且在第二区域上具有不同的纹理。 在蚀刻步骤期间，将氯化物气体前体施加在衬底上，以便在第二区域上移除半导体层。