公开(公告)号：US20090295609A1

公开(公告)日：2009-12-03

申请号：US11760743

申请日：2007-06-09

申请人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。

公开(公告)号：US07821436B2

公开(公告)日：2010-10-26

申请号：US11760743

申请日：2007-06-09

申请人： Venkatesh Teeka Srinvasa Setty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Chakravarthy Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： Venkatesh Teeka Srinvasa Setty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Chakravarthy Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M3/00

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。

公开(公告)号：US07570191B2

公开(公告)日：2009-08-04

申请号：US11760778

申请日：2007-06-10

申请人： Prakash Easwaran ,  Prasun Kali Bhattacharya ,  Venkatesh Teeka Srinivasa Shetty

发明人： Prakash Easwaran ,  Prasun Kali Bhattacharya ,  Venkatesh Teeka Srinivasa Shetty

IPC分类号： H03M1/38

CPC分类号： H03M1/0604 ,  H03M1/168

摘要： Methods and systems for designing a high resolution analog to digital converter (ADC) by eliminating the errors in the ADC stages. An error correction architecture and method eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. Therefore, the constraints of gain and settling of the residue amplifier is significantly reduced.

摘要翻译： 通过消除ADC阶段的错误来设计高分辨率模数转换器（ADC）的方法和系统。 错误校正架构和方法消除了流水线ADC阶段的残差放大器的增益误差和稳定误差。 参考电压误差校正架构和方法消除了ADC中采样动作引起的参考电压误差。 增益误差校正方法使用误差放大器计算增益误差，消除ADC后期的增益误差。 参考电压误差校正方法使用理想的参考电压计算参考电压误差，并在ADC后期校正误差。 因此，残差放大器的增益和稳定的约束显着降低。

公开(公告)号：US07538701B2

公开(公告)日：2009-05-26

申请号：US11760746

申请日：2007-06-09

申请人： Venkatesh Teeka Srinivasa Shetty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Srinivasan Chakravarthy ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： Venkatesh Teeka Srinivasa Shetty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Srinivasan Chakravarthy ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M1/20

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

摘要翻译： 一种通过随机化差分失配来改善模数转换器（ADC）中的动态性能的系统和方法。 通过随机翻转输入信号和输出信号，输入模拟信号的差分失配被随机化。

公开(公告)号：US20070285297A1

公开(公告)日：2007-12-13

申请号：US11760746

申请日：2007-06-09

申请人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M1/12

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

摘要翻译： 一种通过随机化差分失配来改善模数转换器（ADC）中的动态性能的系统和方法。 通过随机翻转输入信号和输出信号，输入模拟信号的差分失配被随机化。