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公开(公告)号：US20250053318A1
公开(公告)日：2025-02-13
申请号：US18932199
申请日：2024-10-30
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Michel Jaouen
IPC: G06F3/06
Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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2.发明授权公开(公告)号：US12190123B2
公开(公告)日：2025-01-07
申请号：US17898312
申请日：2022-08-29
Inventor： Frederic Ruelle , Laurent Meunier , Bechir Jabri , Emmanuel Grandin , Nabil Safi , Ghaith Oueslati , Yohann Martiniault , Jerome Caillet
IPC: G06F9/445 , G06F3/0482 , G06F9/4401 , G06F9/451
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
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公开(公告)号：US12058255B2
公开(公告)日：2024-08-06
申请号：US17553481
申请日：2021-12-16
Inventor： Julien Couvrand , William Orlando
IPC: H04L9/08
CPC classification number: H04L9/0894
Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.
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公开(公告)号：US20240201873A1
公开(公告)日：2024-06-20
申请号：US18531044
申请日：2023-12-06
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Fabien ARRIVE , Yves MAGNAUD
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0679
Abstract: A device executes an authentication process protected by an authentication counter that is incremented in case of an authentication failure. The incrementation of the counter is protected against unexpected device power-off or power-off attacks. A non-volatile memory is divided into pairs of cells. The protecting includes writing a fixed value D into an active pair of two consecutive cells. As long as successful authentications occur, the content of the first cell is overwritten by a random value. When a failed authentication occurs, the content of the second cell is overwritten by a random value and the next two consecutive cells are written with the fixed value D. Those cells form the active pair and the protection process is repeated. This mechanism facilitates preventing the lack of incrementation of the authentication counter in case of unexpected device power-off during the processing of a failed authentication.
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公开(公告)号：US11954548B2
公开(公告)日：2024-04-09
申请号：US17520266
申请日：2021-11-05
Inventor： Frederic Gouabau , Olivier Rouy
IPC: G06K19/07 , G06K19/073 , H05B45/10
CPC classification number: G06K19/07354 , H05B45/10
Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.
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Patent Agency Ranking
公开(公告)号：US11914718B2
公开(公告)日：2024-02-27
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F9/4401 , G06F21/60
CPC classification number: G06F21/575 , G06F9/4403 , G06F21/602 , G06F2221/034
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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7.发明公开公开(公告)号：US20230385420A1
公开(公告)日：2023-11-30
申请号：US18320731
申请日：2023-05-19
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Vincent Berthelot
CPC classification number: G06F21/575 , G06F21/604 , G06F2221/034
Abstract: In an embodiment a method includes executing, during a first phase, one or more first codes stored in a first immutable zone of a non-volatile memory of an electronic device, forbidding, by an access control circuit of the non-volatile memory, execution of any codes stored in a second zone of the non-volatile memory during the first phase, executing, during a second phase, one or more second codes stored in the second zone and forbidding, by the access control circuit, any access to the first zone during the second phase.
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公开(公告)号：US20230315923A1
公开(公告)日：2023-10-05
申请号：US18191598
申请日：2023-03-28
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic Ruelle
Abstract: In an embodiment a method includes detecting, by a monitoring circuit, on a bus of a device during execution by a processor of a code stored in a memory, an address for reading from the memory, wherein the device comprises the processor, the memory, the monitory circuit and the bus coupled to the memory, comparing, by the monitoring circuit, the address with one or more first addresses and controlling, by the monitoring circuit, a clock control circuit to prevent an activation of one or more peripheral circuits when the address is part of the one or more first addresses.
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公开(公告)号：US20230297695A1
公开(公告)日：2023-09-21
申请号：US18179893
申请日：2023-03-07
Inventor： Thierry Biniguer , Benjamin Baratte
CPC classification number: G06F21/602 , G06F21/79
Abstract: In an embodiment a method includes receiving, by a first circuit of a device, a first identifier from a second circuit, generating, by the first circuit, at least one key based on the first identifier, a second identifier of the first circuit and a first key, storing, by the first circuit, the at least one key in a memory of the device, transmitting, by the first circuit, the at least one key to the second circuit and removing, by the first circuit, the at least one key from the memory, wherein the at least one key is generated by the first circuit in response to a request for communication with the second circuit, and wherein the first circuit executes one or more cryptographic operations based on the at least one key.
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10.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC classification number: H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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