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公开(公告)号：US12088429B2
公开(公告)日：2024-09-10
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , H03K7/08 , H04L12/40
CPC classification number: H04L12/403 , H03K7/08 , H04L12/40006 , H04L2012/40215
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US20230300001A1
公开(公告)日：2023-09-21
申请号：US18174387
申请日：2023-02-24
Applicant: STMicroelectronics Application GMBH , STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. , STMicroelectronics S.r.l.
Inventor： Fred Rennig , Jochen Barthel , Ludek Beran , Mirko Dondini , Vaclav Dvorak , Vincenzo Polisi , Marianna Sanza' , CalogeroAndrea Trecarichi , Alfonso Furio
IPC: H04L12/40 , H03K19/00 , H03K17/687
CPC classification number: H04L12/40169 , H03K19/0002 , H03K17/6872 , H03K17/6874 , H04L12/40032 , H04L2012/40273 , H04L2012/40215
Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
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公开(公告)号：US11652457B2
公开(公告)日：2023-05-16
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor Petenyi
CPC classification number: H03F3/45179 , H03F1/0205 , H03F1/301 , H03F2200/78 , H03F2203/45
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
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公开(公告)号：US11526458B2
公开(公告)日：2022-12-13
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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公开(公告)号：US20220159807A1
公开(公告)日：2022-05-19
申请号：US17523641
申请日：2021-11-10
Applicant: STMicroelectronics S.r.l. , STMicroelectronics Application GmbH , STMicroelectronics Design and Application S.R.O.
Inventor： Donato TAGLIAVIA , Vincenzo POLISI , Calogero Andrea TRECARICHI , Francesco Nino MAMMOLITI , Jochen BARTHEL , Ludek BERAN
Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.
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Patent Agency Ranking
公开(公告)号：US20210367456A1
公开(公告)日：2021-11-25
申请号：US16878782
申请日：2020-05-20
Inventor： Michal Toula
Abstract: A wireless charging receiver includes a controller configured to determine that a first overvoltage threshold is met and based thereon enable a first switch to couple an output of a rectifier to electrical ground through a first resistor, to determine that a second overvoltage threshold is met and based thereon enable receive resonant circuit switches to short circuit a receive resonant circuit, to determine that a hysteresis threshold is met and based thereon disable the receive resonant circuit switches to open circuit the receive resonant circuit, and to determine that a hysteresis cycle threshold is met and that the receive resonant circuit switches are disabled and based thereon enable the second switch to couple the second resistor to the electrical ground and to communicate to wireless charging transmitter to decrease the power level on wireless charging receiver side.
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公开(公告)号：US20210357344A1
公开(公告)日：2021-11-18
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
IPC: G06F13/362 , H04L12/40 , G06F11/07
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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公开(公告)号：US20210328563A1
公开(公告)日：2021-10-21
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor PETENYI
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
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公开(公告)号：US20210303504A1
公开(公告)日：2021-09-30
申请号：US17199418
申请日：2021-03-11
Inventor： Rolf Nandlinger , Radek Olexa
Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.
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公开(公告)号：US10788848B2
公开(公告)日：2020-09-29
申请号：US16285330
申请日：2019-02-26
Inventor： Sandor Petenyi
Abstract: An amplifier stage of an LDO regulator circuit includes an amplifier stage that generates a drive signal in response to a first voltage difference an output voltage of the LDO regulator circuit and a reference voltage. A drive stage having a quiescent current consumption is configured to generate a control signal in response to the drive signal. The control signal is applied to the control terminal of a power transistor. A dropout detector senses whether the LDO regulator circuit is operating in closed loop regulation mode or in open loop dropout mode by sensing a second difference in voltage between the drive signal and the control signal. A quiescent current limiter circuit responds to the sensed second difference by controlling the quiescent current consumption of the drive stage, and in particular limiting current consumption when the LDO regulator circuit is operating in the open loop dropout mode.
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