公开(公告)号：US09159828B2

公开(公告)日：2015-10-13

申请号：US13436308

申请日：2012-03-30

Applicant: Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

Inventor： Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7835 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681

Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Abstract translation: 在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道 在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

公开(公告)号：US08816476B2

公开(公告)日：2014-08-26

申请号：US13095539

申请日：2011-04-27

Applicant: Shekar Mallikarjunaswamy

Inventor： Shekar Mallikarjunaswamy

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/74 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L23/495 ,  H01L29/45 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/743 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel.

Abstract translation: 本发明的特征在于形成在其上形成有栅极，源极和漏极区域的半导体衬底上的场效应晶体管，所述栅极区域具有横向栅极沟道。 多个间隔开的沟槽，其各自具有与所述栅极，源极和漏极区域电连通的导电插塞，所述沟槽从所述半导体衬底的后表面延伸到受控的深度。 沟槽接触使源区域和身体区域短路。 源极触点与所述源极区域电连通，漏极触点与所述漏极区域电连通，所述源极和漏极触点设置在所述栅极沟道的相对侧上。

公开(公告)号：US20130075746A1

公开(公告)日：2013-03-28

申请号：US13242970

申请日：2011-09-23

Applicant: Shekar Mallikarjunaswamy ,  François Hébert

Inventor： Shekar Mallikarjunaswamy ,  François Hébert

IPC: H01L29/04 ,  H01L21/331

CPC classification number: H01L29/6625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/735

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract translation: 横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。 使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。 在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。 在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

公开(公告)号：US08098466B2

公开(公告)日：2012-01-17

申请号：US13066907

申请日：2011-04-26

Applicant: Shekar Mallikarjunaswamy

Inventor： Shekar Mallikarjunaswamy

IPC: H02H9/00

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

Abstract translation: 本发明公开了一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在双极结型晶体管（BJT）的发射极和集电极之间的触发齐纳二极管，其中齐纳二极管的反向击穿电压BV小于或等于BJT的BVceo，其中BVceo代表集电极 到发射极击穿电压，基极左开。 TVS电路还包括与BJT并联连接的整流器，用于触发整流器的整流电流，用于进一步限制反向阻断电压的增加。 在优选实施例中，触发齐纳二极管，BJT和整流器通过在N阱和P阱中注入和配置第一和第二导电类型的掺杂区而形成在半导体衬底中，由此TVS可以 作为电子设备的制造过程的一部分并行形成。

公开(公告)号：US20110127602A1

公开(公告)日：2011-06-02

申请号：US12629844

申请日：2009-12-02

Applicant: Shekar Mallikarjunaswamy

Inventor： Shekar Mallikarjunaswamy

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/407 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0617 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/4175 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/732 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/7825 ,  H01L29/7831

Abstract: A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.

Abstract translation: 双通道沟槽LDMOS晶体管包括第一导电类型的衬底; 形成在所述基板上的第二导电类型的半导体层; 形成在所述半导体层中的沟槽栅极形成在所述第一沟槽的上部的第一沟槽; 形成在与所述第一沟槽相邻的所述半导体层中的所述第一导电类型的体区; 所述第二导电类型的源极区域形成在所述体区域中并且邻近所述第一沟槽; 覆盖身体区域的平面门; 所述第二导电类型的漏极区域通过漏极漂移区域与所述体区域间隔开。 平面栅极在体区域中形成横向沟道，并且第一沟槽中的沟槽栅极在LDMOS晶体管的体区中形成垂直沟道。

公开(公告)号：US07851314B2

公开(公告)日：2010-12-14

申请号：US12112120

申请日：2008-04-30

Applicant: Shekar Mallikarjunaswamy ,  Amit Paul

Inventor： Shekar Mallikarjunaswamy ,  Amit Paul

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract translation: 公开了一种短沟道横向MOSFET（LMOS）和方法，其具有用于降低通道导通电阻同时保持高穿透电压的互穿漏极体突起（IDBP）。 LMOS包括较低的器件体积层; 上部源极和上部漏极区域位于下部器件体层的顶部; 上部源极和上部漏极区都与下部器件本体层之间的中间上部区域接触; 上排水区和上体区均形成排水体界面; 排水体接口具有IDBP结构，其中表面排出突起位于掩埋体突起的顶部，同时露出上身体区域的顶部体表面积; 栅极氧化物栅极电极双层，其设置在形成LMOS的上部主体区域的顶部，其具有由在上部源区域和上部漏极区域之间描绘的顶部体表面积的水平长度限定的短沟道长度。

公开(公告)号：US20070001004A1

公开(公告)日：2007-01-04

申请号：US11515179

申请日：2006-08-31

Applicant: Shekar Mallikarjunaswamy ,  Martin Alter

Inventor： Shekar Mallikarjunaswamy ,  Martin Alter

IPC: G06K7/00

CPC classification number: H01L21/761 ,  H01L21/765 ,  H01L21/823481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Abstract translation: 在混合组件，混合信号半导体器件中，提供了与衬底的选择性密封环隔离及其电位，以便将噪声敏感电路与由电噪声电路产生的电噪声隔离。 这种混合使用芯片的适当的预定部分通过与基板的非欧姆接触而从基板隔离，而不损害芯片与划线区域污染的隔离的可靠性。

公开(公告)号：US07145206B2

公开(公告)日：2006-12-05

申请号：US10938311

申请日：2004-09-09

Applicant: Shekar Mallikarjunaswamy

Inventor： Shekar Mallikarjunaswamy

IPC: H01L29/72

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0705 ,  H01L27/0744 ,  H01L29/0692 ,  H01L29/1004 ,  H01L29/7322 ,  H01L29/7378 ,  H01L29/7393

Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.

Abstract translation: MOS场效应晶体管包括在漏极区域中形成的辅助扩散部，其中辅助扩散部具有与漏极区域相反的导电类型并且与漏极区域电短路。 辅助扩散区形成一个寄生双极晶体管，具有减少由正向偏置的漏极到体结的引起的衬底导电的作用。

公开(公告)号：US07064407B1

公开(公告)日：2006-06-20

申请号：US11051520

申请日：2005-02-04

Applicant: Shekar Mallikarjunaswamy

Inventor： Shekar Mallikarjunaswamy

IPC: H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC classification number: H01L27/0727 ,  H01L27/095 ,  H01L27/098 ,  H01L29/0843 ,  H01L29/8083

Abstract: A JFET controlled Schottky barrier diode includes a p-type diffusion region integrated into the cathode of the Schottky diode to form an integrated JFET where the integrated JFET provides on-off control of the Schottky barrier diode. The p-type diffusion region encloses a portion of the forward current path of the Schottky barrier diode where the p-type diffusion region forms the gate of the JFET and the enclosed portion of the forward current path forms the channel region of the JFET. By applying a reverse biased potential to the gate of the JEFT with respect to the anode of the Schottky diode, the forward current of the Schottky diode can be pinched off, thereby providing on-off control over the Schottky diode forward current.

Abstract translation: JFET控制的肖特基势垒二极管包括集成到肖特基二极管的阴极中的p型扩散区，以形成集成JFET，其中集成JFET提供肖特基势垒二极管的导通截止控制。 p型扩散区包围肖特基势垒二极管的正向电流通路的一部分，其中p型扩散区形成JFET的栅极，并且正向电流通路的封闭部分形成JFET的沟道区。 通过相对于肖特基二极管的阳极向JEFT的栅极施加反向偏置电位，可以将肖特基二极管的正向电流夹断，从而对肖特基二极管正向电流进行开关控制。

公开(公告)号：US20060012003A1

公开(公告)日：2006-01-19

申请号：US10889671

申请日：2004-07-13

Applicant: Shekar Mallikarjunaswamy ,  Martin Alter

Inventor： Shekar Mallikarjunaswamy ,  Martin Alter

IPC: H01L29/00

CPC classification number: H01L21/761 ,  H01L21/765 ,  H01L21/823481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.