公开(公告)号：US08237622B2

公开(公告)日：2012-08-07

申请号：US12521244

申请日：2007-12-14

申请人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

发明人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

IPC分类号： H01Q1/36

CPC分类号： H01Q21/29 ,  G06K19/07749 ,  G06K19/07756 ,  G06K19/07779 ,  G06K19/07783 ,  H01Q1/2208 ,  H01Q1/38 ,  H01Q7/00 ,  H01Q9/16 ,  H04B5/00 ,  H04B5/0081

摘要： A base sheet 12 has a structure that stably couples a particular chip measuring 1 mm or less on paper with an antenna line by only disposing the chip and antenna line in such a manner that the chip and antenna line are close to each other, without electrically bringing the chip and antenna line into contact with each other. The base sheet 12 includes a chip 11 having a spiral coil 13 with at least one turn disposed on a surface of the chip, or inside the chip and near the surface thereof and an antenna line 14 having a conductor part 14A orbiting around the coil 13A of the chip 11 or directly over or directly below the coil 13A so that the conductor part is magnetically coupled with the coil 13A. This base sheet has a structure that stably couples even a chip measuring 1 mm or less on paper or the like with an antenna line by only disposing the chip and antenna line in such a manner that the chip and antenna line are close to each other, without physically bringing the chip and antenna line into contact with each other.

摘要翻译： 基片12具有这样的结构，即通过仅将芯片和天线线设置成使得芯片和天线线彼此靠近的方式，将纸上的1mm或更小的特定芯片与天线线连接，而无需电气 使芯片和天线线路相互接触。 基片12包括具有螺旋线圈13的芯片11，其具有设置在芯片的表面上或芯片内部并且在其表面附近的至少一个匝，以及具有围绕线圈13A绕行的导体部件14A的天线线路14 或者直接位于线圈13A的正上方，使得导体部分与线圈13A磁耦合。 这种基片具有如下结构：通过仅使芯片和天线线路彼此靠近的方式设置芯片和天线线，即使将片状或1mm以下的芯片与天线相连， 而不会使芯片和天线相互物理接触。

公开(公告)号：US08178415B2

公开(公告)日：2012-05-15

申请号：US12516493

申请日：2007-11-26

申请人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

发明人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

IPC分类号： H01L21/00

CPC分类号： G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01Q1/2283 ,  H01Q7/005

摘要： A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield is provided.The method for manufacturing RF powder is a method for manufacturing RF powder composed of a large amount of particles 11a each having a substrate 12 and a magnetic coupling circuit device 15. This method includes a step S11 of forming many antenna circuit devices 39 on a wafer 40; a gas dicing step S13 for drawing dicing grooves on a wafer to locate positions of separation of magnetic coupling circuit devices; a protection film formation step S14 for coating surrounding areas of the magnetic coupling circuit devices with a protection film; a reinforcement step S15 for attaching the wafer to a supporting plate using an adhesive sheet; a grinding step S16 for grinding the backside of the wafer until the dicing grooves are reached; and a separation step S17 for separating the circuit devices by removing the supporting plate.

摘要翻译： 一种制造射频粉末的方法，其中RF粉末由大量的颗粒组成并用作集体RF粉末（粉末实体）; 并且可以以稳定的方式从晶片获得大量的RF粉末颗粒，并以高产率提供。 RF粉末的制造方法是由具有基板12和磁耦合电路装置15的大量的粒子11a构成的RF粉末的制造方法。该方法包括在晶片上形成许多天线电路装置39的工序S11 40; 用于在晶片上吸引切割槽的气体切割步骤S13，以定位磁耦合电路器件的分离位置; 保护膜形成步骤S14，用于用保护膜涂覆磁耦合电路装置的周围区域; 加强步骤S15，用于使用粘合片将晶片附着在支撑板上; 用于研磨晶片的背面直到达到切割槽的研磨步骤S16; 以及用于通过移除支撑板来分离电路装置的分离步骤S17。

公开(公告)号：US20110063184A1

公开(公告)日：2011-03-17

申请号：US12521244

申请日：2007-12-14

申请人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

发明人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

IPC分类号： H01Q1/50

CPC分类号： H01Q21/29 ,  G06K19/07749 ,  G06K19/07756 ,  G06K19/07779 ,  G06K19/07783 ,  H01Q1/2208 ,  H01Q1/38 ,  H01Q7/00 ,  H01Q9/16 ,  H04B5/00 ,  H04B5/0081

摘要： A base sheet 12 has a structure that stably couples a particular chip measuring 1 mm or less on paper with an antenna line by only disposing the chip and antenna line in such a manner that the chip and antenna line are close to each other, without electrically bringing the chip and antenna line into contact with each other. The base sheet 12 includes a chip 11 having a spiral coil 13 with at least one turn disposed on a surface of the chip, or inside the chip and near the surface thereof and an antenna line 14 having a conductor part 14A orbiting around the coil 13A of the chip 11 or directly over or directly below the coil 13A so that the conductor part is magnetically coupled with the coil 13A. This base sheet has a structure that stably couples even a chip measuring 1 mm or less on paper or the like with an antenna line by only disposing the chip and antenna line in such a manner that the chip and antenna line are close to each other, without physically bringing the chip and antenna line into contact with each other.

摘要翻译： 基片12具有这样的结构，即通过仅将芯片和天线线设置成使得芯片和天线线彼此靠近的方式，将纸上的1mm或更小的特定芯片与天线线连接，而无需电气 使芯片和天线线路相互接触。 基片12包括具有螺旋线圈13的芯片11，其具有设置在芯片的表面上或芯片内部并且在其表面附近的至少一个匝，以及具有围绕线圈13A绕行的导体部件14A的天线线路14 或者直接位于线圈13A的正上方，使得导体部分与线圈13A磁耦合。 这种基片具有如下结构：通过仅使芯片和天线线以芯片和天线线彼此接近的方式设置芯片和天线线，即使将片状或1mm以下的芯片与天线相连， 而不会使芯片和天线相互物理接触。

公开(公告)号：US20100090925A1

公开(公告)日：2010-04-15

申请号：US12516497

申请日：2007-11-26

申请人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

发明人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fujino ,  Katsuhiko Mishima ,  Susumu Kamihashi

IPC分类号： B05D1/12 ,  H01Q1/40 ,  H01Q1/00

CPC分类号： H01Q1/22 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  G07D7/01 ,  G07D7/04 ,  H01Q1/2208

摘要： A method is provided for adding an RF powder to a sheet-like object having a high property value, such as a variety of cards, paper money, and securities. The RF powder makes it very difficult to produce, for example, counterfeit cards, documents and bills. Also, an RF powder-added base sheet to which the RF powder has been added is provided. In the method for adding the RF powder, the RF powder includes a plurality of RF powder particles 11 and is disposed on a surface of a base sheet 10 to add the RF powder to the base sheet. Each RF powder particle 11 has a magnetic field coupling circuit element in a high frequency magnetic field having a specific frequency. The RF powder is disposed on a surface of a base sheet by a printing technique. The RF powder-added base sheet 10 includes an RF powder including a plurality of RF powder particles 11 disposed within a printed object on a surface of a base sheet. Each RF powder particle 11 has a magnetic field coupling circuit element in a high frequency magnetic field having a high frequency.

摘要翻译： 提供了一种用于将RF粉末添加到诸如各种卡，纸币和证券等具有高属性值的片状物体的方法。 RF粉末很难生产例如伪造卡，文件和纸币。 另外，提供添加了RF粉末的RF粉末添加基片。 在添加RF粉末的方法中，RF粉末包括多个RF粉末颗粒11，并且设置在基片10的表面上，以将RF粉末添加到基片。 每个RF粉末颗粒11具有在具有特定频率的高频磁场中的磁场耦合电路元件。 RF粉末通过印刷技术设置在基片的表面上。 RF粉末添加基片10包括RF基片，其包括设置在基片的表面上的印刷对象物内的多个RF粉末粒子11。 每个RF粉末颗粒11在具有高频率的高频磁场中具有磁场耦合电路元件。

公开(公告)号：US20100067166A1

公开(公告)日：2010-03-18

申请号：US12516643

申请日：2007-11-26

申请人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fukino ,  Katsuhiko Mishima ,  Susumu Kamihashi

发明人： Yuji Furumura ,  Naomi Mura ,  Shinji Nishihara ,  Katsuhiro Fukino ,  Katsuhiko Mishima ,  Susumu Kamihashi

IPC分类号： H03H7/00 ,  G05B19/00

CPC分类号： H04B5/0012 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  G07D7/01 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q7/005 ,  H04B5/0081 ,  H04B5/02

摘要： Provided are an RF powder particle, an RF powder, and an RF powder-containing base that can make it difficult to fabricate, for example, forged documents or forged bank notes with respect to sheet-like objects having high proprietary values, such as bank notes, and that allow necessary information to be stored in each of the large number of particles which are each provided with a tank circuit having a predetermined resonant frequency.The RF powder particle includes a coil 24 (inductance element) as a magnetic filed coupling element and a condenser 25 (capacitance element) connected to the both ends of the coil on an insulating surface of a substrate 22 and is configured so as to form a tank circuit 31 by the inductance element and the capacitance element. The tank circuit 31 functions as a circuit in a resonance state or in a non-resonance state in accordance with conditions in response to a high-frequency magnetic field from outside.

摘要翻译： 提供了RF粉末颗粒，RF粉末和含RF粉末的基底，其可以使得难以制造例如伪造文件或伪造钞票相对于具有高专利价值的片状物体，例如银行 并且允许将必要的信息存储在每个具有预定谐振频率的储能电路的大量颗粒中。 RF粉末颗粒包括作为磁场耦合元件的线圈24（电感元件）和在基板22的绝缘表面上连接到线圈两端的电容器25（电容元件），并且被构造成形成 电容元件和电容元件构成。 储能电路31根据来自外部的高频磁场的条件，作为谐振状态或非共振状态的电路发挥作用。

公开(公告)号：US20090198878A1

公开(公告)日：2009-08-06

申请号：US12363940

申请日：2009-02-02

申请人： Shinji NISHIHARA ,  Eiji NAGATA

发明人： Shinji NISHIHARA ,  Eiji NAGATA

IPC分类号： G06F12/02

CPC分类号： G06F11/1666 ,  G06F11/1417 ,  G06F11/18

摘要： The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs. While an instruction has been contained in the second program, the instruction instructs that the plurality of first programs are transferred from the first storage device to the second storage device, contents of the plurality of first programs transferred to the second storage devices are compared with each other; and if the contents of the plurality of first programs are not made coincident with each other, then a normal program is judged from the plurality of first programs based upon a majority decision. The CPU executes the first program judged as the normal program so as to initially initiate the information processing system.

摘要翻译： 信息处理系统包括：第一非易失性存储装置，其中用于启动信息处理系统的多个第一程序和多个第一程序的复制已经以彼此不同的块存储; 第二易失性存储设备，所述多个第一程序被传送到所述第二易失性存储设备; 存储用于执行所述多个第一节目的第二节目的第三非易失性存储装置; 以及用于执行多个第一程序的CPU（中央处理单元）。 当在第二程序中包含指令时，指令指示多个第一程序从第一存储设备传送到第二存储设备，将传送到第二存储设备的多个第一程序的内容与每个 其他; 并且如果多个第一节目的内容不一致，则根据多数决定从多个第一节目中判断正常节目。 CPU执行被判断为正常程序的第一程序，以便最初启动信息处理系统。

公开(公告)号：US07553766B2

公开(公告)日：2009-06-30

申请号：US11950152

申请日：2007-12-04

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/44

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US07241685B2

公开(公告)日：2007-07-10

申请号：US10390413

申请日：2003-03-18

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara

IPC分类号： H01L21/44

CPC分类号： H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

摘要翻译： 提供一种具有降低短路可能性的布线结构的半导体器件及其制造方法。 此外，提供了具有高可靠性的半导体器件。 此外，提供了一种具有高产率的半导体器件。 在半导体衬底的一个主表面侧形成布线，并且具有相邻导体层和主布线层的叠层结构。 主配线层包含一个添加的元素以防止迁移。 相邻的导体层由用于防止主要构成元素和主配线层的添加元素扩散到相邻导体层下方的基板中的材料形成，并且添加元素在靠近界面处的位置的浓度 与相邻的导体层间隔开的主配线层的添加元素的浓度相比，相邻的导体层和主布线层的电位低。

公开(公告)号：US06858484B2

公开(公告)日：2005-02-22

申请号：US10721902

申请日：2003-11-26

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/532 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 通过使用高纯度Co靶通过溅射将沉积在晶片的主平面上的Co膜进行硅化，在MOSFET的栅极，源极和漏极的表面上形成具有低电阻和小的结漏电流的Co硅化物层 Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US06656828B1

公开(公告)日：2003-12-02

申请号：US09869045

申请日：2001-06-22

申请人： Touta Maitani ,  Shinji Nishihara

发明人： Touta Maitani ,  Shinji Nishihara

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76873 ,  H01L24/11 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014

摘要： A CSP in which bump electrodes (2) arranged in an area on a chip (1A) and bonding pads (BP) are electrically connected to each other via Cu interconnections (6), wherein the surface of the Cu interconnection (6) is covered with a barrier layer (14) to thereby prevent diffusion of Cu from the CU interconnection (6) into a polyimide resin layer (3) by a heat treatment during the manufacturing process.

摘要翻译： 布置在芯片（1A）和接合焊盘（BP）的区域中的凸块电极（2）通过Cu互连（6）彼此电连接的CSP，其中Cu互连（6）的表面被覆盖 具有阻挡层（14），从而防止Cu在制造过程中通过热处理从Cu互连（6）扩散到聚酰亚胺树脂层（3）中。