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公开(公告)号：US20110122693A1
公开(公告)日：2011-05-26
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。
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2.发明授权Apparatus and method for generating wide-range regulated supply voltages for a flash memory 有权用于产生用于闪速存储器的宽范围稳压电源电压的装置和方法公开(公告)号：US07848167B2
公开(公告)日：2010-12-07
申请号：US12255622
申请日：2008-10-21
申请人： Soo-yong Park , Boon-Aik Ang , Steve Choi
发明人： Soo-yong Park , Boon-Aik Ang , Steve Choi
摘要： A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
摘要翻译： 提供电压调节器。 电压调节器提供与数字多位选择信号成比例的输出电压。 电压调节器包括粗调电压调节器和精密电压调节器。 粗电压调节器基于基于选择信号的最高有效位选择的分压器的输出提供粗略的输出电压。 精细电压调节器提供粗输出电压的输出电压。 微调电压调节器的输出通过调节可调电流源的输出来调节，该可调电流源提供给耦合在输出端和精密电压调节器的一个输入端之间的电阻器。
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3.发明授权公开(公告)号：US07663921B2
公开(公告)日：2010-02-16
申请号：US12267519
申请日：2008-11-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.
摘要翻译： 公开了包括排列在扇区中的存储单元的系统和方法。 在一个示例性实施方案中，每个存储单元可以包括顶部栅极，源极，耦合扇区中的存储器单元的顶栅极线和将存储器单元耦合在一起的字线。 此外，顶栅线可以动态耦合到字线。 其它示例性实现可涉及用于驱动字线和/或顶栅线，多电平存储器单元和/或浮栅线特征的驱动器。
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4.发明授权Flash memory array having control/decode circuitry for disabling top gates of defective memory cells 有权闪存阵列具有控制/解码电路，用于禁止有缺陷的存储器单元的顶栅公开(公告)号：US07567458B2
公开(公告)日：2009-07-28
申请号：US11235901
申请日：2005-09-26
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。
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公开(公告)号：US20090067239A1
公开(公告)日：2009-03-12
申请号：US12267519
申请日：2008-11-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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公开(公告)号：US20090052248A1
公开(公告)日：2009-02-26
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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7.发明授权Circuit and a method to screen for defects in an addressable line in a non-volatile memory 有权电路和一种在非易失性存储器中筛选可寻址线路中的缺陷的方法公开(公告)号：US06972994B2
公开(公告)日：2005-12-06
申请号：US10797156
申请日：2004-03-09
申请人： Hung Q. Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
发明人： Hung Q. Nguyen , Steve Choi , Loc Hoang , Alexander Kotov
CPC分类号： G11C29/024
摘要： A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要翻译： 用于屏蔽非易失性存储器阵列中可寻址线路中的缺陷的电路包括具有多个镜像级的电流镜电路。 电流镜电路连接到可寻址线路并接收控制信号并镜像控制信号以向可寻址线路提供电流。 在优选实施例中，电流镜电路向可寻址线路提供高电压电流，该可寻址线路用于对连接到可寻址线路的存储器单元实现诸如编程或擦除的操作。 连接到可寻址线路的存储器单元的状态变化或不存在状态的变化可用于筛选可寻址线路中的缺陷。
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公开(公告)号：US08270213B2
公开(公告)日：2012-09-18
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/12
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。
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公开(公告)号：US07778080B2
公开(公告)日：2010-08-17
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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10.发明申请APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY 有权用于产生FLASH存储器的宽范围调节电源电压的装置和方法公开(公告)号：US20100097876A1
公开(公告)日：2010-04-22
申请号：US12255622
申请日：2008-10-21
申请人： Soo-Yong Park , Boon-Aik Ang , Steve Choi
发明人： Soo-Yong Park , Boon-Aik Ang , Steve Choi
摘要： A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
摘要翻译： 提供电压调节器。 电压调节器提供与数字多位选择信号成比例的输出电压。 电压调节器包括粗调电压调节器和精密电压调节器。 粗电压调节器基于基于选择信号的最高有效位选择的分压器的输出提供粗略的输出电压。 精细电压调节器提供粗输出电压的输出电压。 微调电压调节器的输出通过调节可调电流源的输出来调节，该可调电流源提供给耦合在输出端和精密电压调节器的一个输入端之间的电阻器。
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