摘要:
A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要:
A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.
摘要:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要:
A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
摘要:
A valve system comprising a closure member that is linearly translatable within a valve body. A hydraulic override assembly comprises a first end that is connected to the valve body and a first rod member that is connected to the closure member. A linear actuator is connected to a second end of the hydraulic override assembly and comprises a second rod member that is operable to move the first rod member.
摘要:
An apparatus that includes a body of a gate configured to seal a gate valve. In certain embodiments, the body has a first face with a first coating disposed thereon, and a second face opposite the first face and having a second coating disposed thereon. The body also may include a flow bore that extends from the first face, through the body of the gate, to the second face and a reference structure that does not have either the first coating or the second coating disposed thereon. In some embodiments, the reference structure is configured to define a plane on the first face, the second face, or both during a planarization process.
摘要:
A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要:
A valve system comprising a closure member that is linearly translatable within a valve body. A fail safe assembly is connected to the valve body and a first rod member that is connected to the closure member. A linear actuator is movably connected to the fail safe assembly and is operable to move the first rod member. A mechanical override system is connected to the linear actuator and is operable to move the linear actuator relative to the valve body.