公开(公告)号：US20100103760A1

公开(公告)日：2010-04-29

申请号：US12258747

申请日：2008-10-27

Applicant: Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

Inventor： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC: G11C5/14 ,  G11C8/00

CPC classification number: G11C5/147

Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

Abstract translation: 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US07639056B2

公开(公告)日：2009-12-29

申请号：US11138788

申请日：2005-05-26

Applicant: Sumanth Katte Gururajarao ,  Hugh T. Mair ,  David B. Scott ,  Uming Ko

Inventor： Sumanth Katte Gururajarao ,  Hugh T. Mair ,  David B. Scott ,  Uming Ko

IPC: H03K3/289 ,  H03K3/356

CPC classification number: H03K3/356008 ,  H04W52/0283 ,  Y02D70/122

Abstract: In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Abstract translation: 在用于数据保持的方法和系统中，数据输入由第一锁存器锁存。 耦合到第一锁存器的第二锁存器接收用于保持的数据输入，而在备用电源模式下第一锁存器不工作。 第一个锁存器在待机电源模式期间从关闭的第一电源线接收电力。 第二锁存器从第二电源线接收电力。 控制器接收时钟输入和保持信号，并向第一锁存器和第二锁存器提供时钟输出。 保持信号的改变表示转变到待机功率模式。 控制器继续将时钟输出保持在预定的电压电平，并且第二锁存器在待机功率模式下继续从第二电源线接收电力，从而保留数据输入。

公开(公告)号：US20070223294A1

公开(公告)日：2007-09-27

申请号：US11385151

申请日：2006-03-21

Applicant: Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

Inventor： Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

IPC: G11C7/00

CPC classification number: G11C8/10

Abstract: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Abstract translation: 一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。 存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。 控制逻辑向存储器提供目标位单元的地址。 在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

公开(公告)号：US07162652B2

公开(公告)日：2007-01-09

申请号：US10739469

申请日：2003-12-18

Applicant: Sami Issa ,  Uming Ko ,  Baher Haroun ,  David Scott

Inventor： Sami Issa ,  Uming Ko ,  Baher Haroun ,  David Scott

IPC: G06F1/00 ,  G06F1/32 ,  G01R31/02

CPC classification number: G06F1/3243 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A power management system (12) in an electronic device (10). The system comprises circuitry (14x), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CPx). The system alternatively or cumulatively also comprises circuitry (22x) for indicating a potential capability of operational speed of the data path and/or circuitry (24x) for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry (26) for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.

Abstract translation: 电子设备（10）中的电源管理系统（12）。 响应于至少一个系统参数，该系统包括用于提供数据处理功能的电路（14XX），其中用于提供数据处理功能的电路包括数据路径（CP SUB>）。 该系统可替代地或累积地还包括用于指示用于指示数量的数据路径和/或电路（24×x×）的操作速度的潜在能力的电路（22XX） 用于提供数据处理功能的电路的电流泄漏。 该系统还包括用于响应于用于指示潜在能力的电路中的一个或两者以及用于指示电流泄漏量的电路来调整至少一个系统参数的电路（26）。

公开(公告)号：US07091766B2

公开(公告)日：2006-08-15

申请号：US10616207

申请日：2003-07-03

Applicant: Uming Ko ,  David B. Scott ,  Sumanth Gururajarao ,  Hugh Mair

Inventor： Uming Ko ,  David B. Scott ,  Sumanth Gururajarao ,  Hugh Mair

IPC: H03K3/12 ,  H03K3/37 ,  H03K3/286 ,  H03K3/356

CPC classification number: H03K3/356008

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.

Abstract translation: 提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作， 用于实现状态保留功能。 此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

公开(公告)号：US5955912A

公开(公告)日：1999-09-21

申请号：US736465

申请日：1996-10-24

Applicant: Uming Ko

Inventor： Uming Ko

IPC: H03K17/693 ,  H03K17/62

CPC classification number: H03K17/693

Abstract: A multiplexer has first, second, third and fourth inputs receiving respective first, second, third and fourth input signals, having first and second control inputs receiving respective first and second select input signals and an output. Each of the four input signals is supplied to the input of a CMOS transmission gate. The first and second transmission gates are clocked via the first select signal and its inverse in a first phase. The third and fourth transmission gates are clocked via the first select signal and its inverse in a second phase, opposite to the first phase. A first embodiment includes a first intermediate inverter having an input connected jointly to the outputs of the first and second transmission gates and a second intermediate inverter having an input connected jointly to the outputs of the third and fourth transmission gates. The multiplexer output is provides by a fifth and a sixth transmission gate oppositely clocked via the second control signal input and coupled to the first and second intermediate inverters, respectively. A second embodiment employs double pass logic in place of the fifth and sixth transmission gates and an output inverter. A third embodiment employs two oppositely clocked tristate inverters for output. A fourth embodiment employs N-type MOSFETs instead of transmission gates. A P-type MOSFET provides feedback to an output inverter to reduce possible static power dissipation.

Abstract translation: 多路复用器具有接收相应的第一，第二，第三和第四输入信号的第一，第二，第三和第四输入，具有接收相应的第一和第二选择输入信号的第一和第二控制输入和输出。 四个输入信号中的每一个被提供给CMOS传输门的输入端。 第一和第二传输门经由第一选择信号及其在第一阶段中的反相来计时。 第三和第四传输门经由第一选择信号及其与第一相位相反的第二阶段的反相来计时。 第一实施例包括具有与第一和第二传输门的输出共同连接的输入的第一中间反相器和具有与第三和第四传输门的输出共同连接的输入的第二中间反相器。 多路复用器输出由第五和第六传输门提供，第五和第六传输门通过输入的第二控制信号相反时钟，并分别耦合到第一和第二中间反相器。 第二实施例采用双通逻辑代替第五和第六传输门和输出反相器。 第三实施例采用两个相反时钟的三态反相器进行输出。 第四实施例采用N型MOSFET而不是传输门。 P型MOSFET为输出反相器提供反馈，以减少可能的静态功耗。

公开(公告)号：US20110216619A1

公开(公告)日：2011-09-08

申请号：US13106612

申请日：2011-05-12

Applicant: Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

Inventor： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

Abstract translation: 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US07570100B2

公开(公告)日：2009-08-04

申请号：US10918869

申请日：2004-08-16

Applicant: Wei Dong ,  Hiep Tran ,  Hugh T. Mair ,  Uming Ko

Inventor： Wei Dong ,  Hiep Tran ,  Hugh T. Mair ,  Uming Ko

IPC: H03K17/687

CPC classification number: H03K19/00346 ,  H03K17/166 ,  H03K17/167 ,  H03K17/687 ,  H03K19/0016

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Abstract translation: 为电路提供电源同时避免大的瞬态电流的系统和方法。 优选实施例包括具有将电源耦合到电路的多个开关（例如开关405）的分布式开关（例如开关装置400）。 每个开关由控制信号单独控制，并依次打开。 还耦合到每个开关是预驱动器电路（例如预驱动器电路410）。 预驱动电路包括一个电位调节电路（例如电位调节电路505），其快速地调节开关处的电压电位;以及速率调节电路（例如速率调整电路520），其加速横跨 一旦瞬态电流不再需要切换， 调整电压电位以使开关工作在饱和模式，从而增加开关两端的有效电容，从而延迟开关上的功率上升。

公开(公告)号：US20090039952A1

公开(公告)日：2009-02-12

申请号：US11947012

申请日：2007-11-29

Applicant: Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

Inventor： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC: G05F1/10 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/78

Abstract: A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

Abstract translation: 一种方法包括解析集成电路的设计以定义自动功率选通电源域中的单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US20060125470A1

公开(公告)日：2006-06-15

申请号：US11010135

申请日：2004-12-10

Applicant: Wei Chen ,  Hugh Mair ,  Uming Ko ,  David Scott

Inventor： Wei Chen ,  Hugh Mair ,  Uming Ko ,  David Scott

IPC: G01R31/28

CPC classification number: G01R31/3008 ,  G01R31/3012

Abstract: System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

Abstract translation: 通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。 优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如， 开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断 。