公开(公告)号：US09344099B2

公开(公告)日：2016-05-17

申请号：US14061529

申请日：2013-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Buckler

IPC: G01R25/00 ,  H03D13/00 ,  H03L7/193 ,  H03L7/091 ,  H03L7/087

CPC classification number: H03L7/193 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/0012

Abstract: Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Abstract translation: 描述了用于使用数字频率测量电路阵列连续测量异步同步系统的发射和接收时钟域之间的频率比的方法的实施例，所述数字频率测量电路在单个频率测量所需的单个计数器周期内提供重叠的频率和检测间隔测量 电路完成频率测量。 实施例可以用在预测同步器中，以便为使用频率漂移或斜坡降低功耗和过热条件的片上系统（SOC）器件提供低等待时间的连续频率测量。

公开(公告)号：US20150188649A1

公开(公告)日：2015-07-02

申请号：US14146654

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

IPC: H04J3/06

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

公开(公告)号：US20150117582A1

公开(公告)日：2015-04-30

申请号：US14064045

申请日：2013-10-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Buckler ,  SUDHA THIRUVENGADAM

IPC: H04L7/033

CPC classification number: H04L7/0331 ,  G06F1/12 ,  H03J1/005 ,  H03L7/00 ,  H04L7/0012

Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

Abstract translation: 描述了实现方案和系统，使得能够将来自时钟控制器的更新直接发送到预测同步器以管理发射和接收时钟域之间的频率的即时变化，包括从锁相环电路接收接收和发送参考频率 从耦合到锁相环电路的控制器接收和发送恒定码，获得延时因子以适应发射和接收时钟域之间的相位检测，并使用时间延迟因子计算新的检测间隔和频率信息， 参考频率和常数码。

公开(公告)号：US09294263B2

公开(公告)日：2016-03-22

申请号：US14146654

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

IPC: H04J3/06 ,  H04L7/02 ,  G06F1/12 ,  H04W56/00 ,  H04L7/033

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

公开(公告)号：US09143315B2

公开(公告)日：2015-09-22

申请号：US14064045

申请日：2013-10-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Buckler ,  Sudha Thiruvengadam

IPC: H03D3/24 ,  H04L7/033

CPC classification number: H04L7/0331 ,  G06F1/12 ,  H03J1/005 ,  H03L7/00 ,  H04L7/0012

Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

Abstract translation: 描述了实现方案和系统，使得能够将来自时钟控制器的更新直接发送到预测同步器以管理发射和接收时钟域之间的频率的即时变化，包括从锁相环电路接收接收和发送参考频率 从耦合到锁相环电路的控制器接收和发送恒定码，获得延时因子以适应发射和接收时钟域之间的相位检测，并使用时间延迟因子计算新的检测间隔和频率信息， 参考频率和常数码。

公开(公告)号：US20150109028A1

公开(公告)日：2015-04-23

申请号：US14061529

申请日：2013-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Buckler

IPC: H03L7/193 ,  H03L7/087 ,  H03L7/091

CPC classification number: H03L7/193 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/0012

Abstract: Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Abstract translation: 描述了用于使用数字频率测量电路阵列连续测量异步同步系统的发射和接收时钟域之间的频率比的方法的实施例，所述数字频率测量电路在单个频率测量所需的单个计数器周期内提供重叠的频率和检测间隔测量 电路完成频率测量。 实施例可以用在预测同步器中，以便为使用频率漂移或斜坡降低功耗和过热条件的片上系统（SOC）器件提供低等待时间的连续频率测量。

公开(公告)号：US08847647B1

公开(公告)日：2014-09-30

申请号：US14024396

申请日：2013-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Buckler

IPC: H03L7/00 ,  H03K3/356

CPC classification number: H03K3/0375

Abstract: An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.

Abstract translation: 输入信号和复位信号提供给可复位触发器的相应输入。 可复位触发器产生输出信号。 响应于输入信号的相应转换和响应于复位信号的断言从第二逻辑状态转换到第一逻辑状态，输出信号从第一逻辑状态转换到第二逻辑状态。 响应于从第二逻辑状态到第一逻辑状态的输入信号的转变而断言警告信号。 当警告信号被解除置位时，逻辑门转发输出信号，并响应于警告信号的断言而提供处于第一逻辑状态的信号。