中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.022 seconds)

    METHODS AND SYSTEMS OF SYNCHRONIZER SELECTION
    2.
    发明申请
    METHODS AND SYSTEMS OF SYNCHRONIZER SELECTION 有权
    同步选择方法与系统

    公开(公告)号：US20150188649A1

    公开(公告)日：2015-07-02

    申请号：US14146654

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

    IPC: H04J3/06

    CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

    Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

    Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

    CONTROL OF THERMAL ENERGY TRANSFER FOR PHASE CHANGE MATERIAL IN DATA CENTER
    3.
    发明申请
    CONTROL OF THERMAL ENERGY TRANSFER FOR PHASE CHANGE MATERIAL IN DATA CENTER 审中-公开
    数据中心相变材料热能转移控制

    公开(公告)号：US20160338230A1

    公开(公告)日：2016-11-17

    申请号：US14709655

    申请日：2015-05-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Fulya Kaplan ,  Manish Arora ,  Wayne P. Burleson ,  Indrani Paul ,  Yasuko Eckert

    IPC: H05K7/20

    CPC classification number: H05K7/20809 ,  H05K5/0213

    Abstract: A cooling system controller for a set of computing resources of a data center includes a first interface to couple to a first flow controller that controls a rate of thermal energy transfer to a PCM store from the set of computing resources, a second interface to couple to a second flow controller that controls a rate of thermal energy transfer from the PCM store to a cooling system, and a controller to determine a current set of operational parameters for the data center and to manipulate the first and second flow controllers and via the first and second interfaces to control a net thermal energy transfer to and from the PCM store based on the current set of parameters.

    Abstract translation: 用于数据中心的一组计算资源的冷却系统控制器包括耦合到第一流控制器的第一接口，该第一接口控制从该组计算资源到PCM存储器的热能传输速率，第二接口耦合到 第二流量控制器，其控制从PCM存储器到冷却系统的热能传递速率;以及控制器，用于确定数据中心的当前操作参数集合，并且操纵第一和第二流量控制器，并经由第一和第二流控制器 第二接口，用于基于当前的参数集来控制到/或从PCM存储器的净热能传递。

    Methods and systems of synchronizer selection
    4.
    发明授权
    Methods and systems of synchronizer selection 有权
    同步器选择方法与系统

    公开(公告)号：US09294263B2

    公开(公告)日：2016-03-22

    申请号：US14146654

    申请日：2014-01-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

    IPC: H04J3/06 ,  H04L7/02 ,  G06F1/12 ,  H04W56/00 ,  H04L7/033

    CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

    Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

    Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE
    5.
    发明申请
    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE 审中-公开
    异步时序域在处理设备中的功率和性能管理

    公开(公告)号：US20160077545A1

    公开(公告)日：2016-03-17

    申请号：US14489130

    申请日：2014-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wayne P. Burleson ,  Manish Arora ,  Indrani Paul ,  Yasuko Eckert

    IPC: G06F1/08 ,  G06F1/26

    CPC classification number: G06F1/12 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

    Abstract translation: 处理装置包括在第一定时域中的产生处理器单元和与第一定时域异步的第二定时域中的消耗处理器单元。 队列用于在生成处理器单元和消费处理器单元之间传送数据。 系统管理单元基于队列的丰满度的变化率来修改生成处理器单元或消费处理器单元中的一个或两个的操作频率或工作电压中的一个或两个。

Patent Agency Ranking