公开(公告)号：US12174743B2

公开(公告)日：2024-12-24

申请号：US17643732

申请日：2021-12-10

Applicant: Arm Limited

Inventor： Graeme Leslie Ingram ,  Michael Jean Sole ,  Erik Persson

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1081 ,  G06N3/02

Abstract: A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

公开(公告)号：US11580402B2

公开(公告)日：2023-02-14

申请号：US16871785

申请日：2020-05-11

Applicant: Arm Limited

Inventor： Erik Persson ,  Sven Ola Johannes Hugosson

IPC: G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H03M7/30 ,  H03M7/40 ,  G06N20/00

Abstract: A method for adapting a trained neural network is provided. Input data is input to the trained neural network and a plurality of filters are applied to generate a plurality of channels of activation data. Differences between corresponding activation values in the plurality of channels of activation data are calculated and an order of the plurality of channels is determined based on the calculated differences. The neural network is adapted so that it will output channels of activation data in the determined order. The ordering of the channels of activation data is subsequently used to compress activation data values by taking advantage of a correlation between activation data values in adjacent channels.

公开(公告)号：US20170061577A1

公开(公告)日：2017-03-02

申请号：US15238873

申请日：2016-08-17

Applicant: ARM Limited

Inventor： Michal Bogusz ,  Erik Persson

IPC: G06T3/40

CPC classification number: G06T3/40 ,  G06T1/60

Abstract: A scaling apparatus for scaling data arrays, such as images, comprises first horizontal scaling stage circuitry operable to scale a data array input to the scaling apparatus in the horizontal direction, one or more line memories for storing horizontal lines for a data array, wherein the or each line memory is for storing a horizontal line of data for the data array, vertical scaling stage circuitry operable to read data stored in the one or more line memories and to scale the read data in the vertical direction, and second horizontal scaling stage circuitry operable to scale a data array in the horizontal direction.

Abstract translation: 用于缩放数据阵列（诸如图像）的缩放装置包括可操作以在水平方向上缩放输入到缩放设备的数据阵列的第一水平缩放级电路，用于存储用于数据阵列的水平线的一个或多个行存储器，其中， 或者每行存储器用于存储用于数据阵列的水平线数据，垂直缩放级电路可操作以读取存储在一个或多个行存储器中的数据，并在垂直方向上缩放读数据;以及第二水平缩放级电路 可操作以在水平方向上缩放数据阵列。

公开(公告)号：US12159223B2

公开(公告)日：2024-12-03

申请号：US17084249

申请日：2020-10-29

Applicant: Arm Limited

Inventor： Davide Marani ,  Erik Persson ,  Viet-Hoa Do ,  Dan Staffan Henrik Johansson

IPC: G06N3/08 ,  G06F7/76 ,  G06F17/16 ,  G06N3/063

Abstract: A method of processing image data of a neural network is performed by a data processing apparatus and comprises writing a first tensor to first storage of the data processing apparatus using a row stride, wherein the first tensor comprises at least one data group, the at least one data group comprising a plurality of data samples and having height, width, and depth dimensions [h, w, c]. The method further comprises transforming the first tensor into a second tensor using a first stride such that the second tensor is a column tensor comprising a plurality of rows, and writing the second tensor to second storage using a second stride that is related to a multiple of the first stride, δn, such that the second stride covers a first set of memory elements in the second storage into which data samples of a first row of the second tensor are stored and a second set of memory elements into which no data samples from the second tensor are stored.

公开(公告)号：US12001369B2

公开(公告)日：2024-06-04

申请号：US17709293

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

公开(公告)号：US20230315670A1

公开(公告)日：2023-10-05

申请号：US17709293

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

公开(公告)号：US10938411B1

公开(公告)日：2021-03-02

申请号：US16829879

申请日：2020-03-25

Applicant: Arm Limited

Inventor： Derek David Whiteman ,  Erik Persson ,  Tomas Fredrik Edsö

IPC: H03M7/40 ,  H03M7/30 ,  G06N3/02

Abstract: A method for compressing activation data of a neural network to be written to a storage is provided. The activation data is formed into a plurality of groups and a state indicator indicates whether there are any data elements within each group that have a non-zero value. A second state indicator indicates, for groups having a non-zero value, whether sub-groups within the group contain a data element having a non-zero value. A sub-group state indicator indicates, for each sub-group having a non-zero value, which data elements within that sub-group have a non-zero value. Non-zero values of data elements in the activation data are encoded and a compressed data set is formed comprising the first state indicators, any second state indicators, any sub-group state indicators and the encoded non-zero values.

公开(公告)号：US20190196745A1

公开(公告)日：2019-06-27

申请号：US16226584

申请日：2018-12-19

Applicant: Arm Limited

Inventor： Erik Persson ,  Stefan Johannes Frid ,  Philip Gregory Hall ,  Dominic Hugo Symes ,  Sven Ola Johannes Hugosson ,  Robert Norberg

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673

Abstract: A producer processing unit of a data processing system that is producing a stream of data for use by one or more consumer processing units of the data processing system maintains a record that is accessible to the consumer processing units of a position in the data stream for which it has written data to memory. The consumer processing units then control their reading of the data stream from the memory in accordance with the write position record maintained by the producer processing unit.

公开(公告)号：US09213650B2

公开(公告)日：2015-12-15

申请号：US14560464

申请日：2014-12-04

Applicant: ARM Limited

Inventor： Erik Persson ,  Ola Hugosson ,  Andreas Bjorklund

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1018 ,  G06F12/1027 ,  G06F12/122

Abstract: A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Abstract translation: 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US10148963B2

公开(公告)日：2018-12-04

申请号：US15274044

申请日：2016-09-23

Applicant: ARM Limited

Inventor： Erik Persson ,  Fredrik Peter Stolt

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/137 ,  H04N19/105 ,  H04N19/513 ,  H04N19/86 ,  H04N19/59 ,  H04N19/172 ,  H04N19/176 ,  H04N19/182

Abstract: To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a second resolution that is finer than the first resolution. The estimated second, finer position resolution difference measures are then used to select a set of reference frame block positions for which to determine “full” difference measures. The determined “full” difference measures for each of the selected reference frame block positions are then used to select the reference frame block position to use when encoding the frame block and a motion vector corresponding to that reference frame block position is associated with and encoded for the frame block being encoded.