公开(公告)号：US11967365B2

公开(公告)日：2024-04-23

申请号：US16898401

申请日：2020-06-10

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Bikas Maiti ,  Venu Anantuni ,  Martin Jay Kinkade

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.

公开(公告)号：US09070431B2

公开(公告)日：2015-06-30

申请号：US14063612

申请日：2013-10-25

Applicant: ARM LIMITED

Inventor： Frank Guo ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。

公开(公告)号：US09064559B2

公开(公告)日：2015-06-23

申请号：US13967879

申请日：2013-08-15

Applicant: ARM LIMITED

Inventor： Bikas Maiti ,  Yew Keong Chong ,  Martin Jay Kinkade

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/148 ,  G11C7/227 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

Abstract translation: 存储器件包括布置成多个行和列的存储器单元的阵列，多个字线，每个字线耦合到相关行的存储器单元，以及多个位线，每个位线耦合到 相关的存储单元列。 访问电路被耦合到字线和位线，以便对阵列内的所选存储单元执行访问操作。 控制电路控制接入电路的操作，并且包括自定时路径（STP）延迟电路。 控制电路在控制访问电路执行所述访问操作时采用延迟指示。 电压供应控制电路根据控制信号将外部电压源和阵列电压电源之间的电压供应切换到STP延迟电路的至少一部分。

公开(公告)号：US09620200B1

公开(公告)日：2017-04-11

申请号：US15081869

申请日：2016-03-26

Applicant: ARM Limited

Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

公开(公告)号：US20150117119A1

公开(公告)日：2015-04-30

申请号：US14063612

申请日：2013-10-25

Applicant: ARM LIMITED

Inventor： Frank GUO ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。

公开(公告)号：US08645893B1

公开(公告)日：2014-02-04

申请号：US13658072

申请日：2012-10-23

Applicant: ARM Limited

Inventor： Gus Yeung ,  Martin Jay Kinkade ,  Marlin Wayne Frederick, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract translation: 公开了一种生成集成电路的布局的方法，该布局包括标准单元和由存储器编译器生成的至少一个存储器实例，以定义集成电路的存储器件。 接收指定所需存储器实例的一个或多个属性的输入数据。 内存编译器基于输入数据并使用指定的内存架构生成所需的内存实例。 提供了一个标准的细胞库。 内存编译器引用标准单元库的至少一个属性，以便生成所需的内存实例。 然后通过用从标准单元库中选择的标准单元格填充标准单元行来生成布局，以便提供集成电路所需的功能组件，并将由存储器编译器提供的所需存储器实例集成到布局中。