公开(公告)号：US09997217B1

公开(公告)日：2018-06-12

申请号：US15477516

申请日：2017-04-03

Applicant: ARM Limited

Inventor： Ankur Goel ,  Munish Kumar ,  Nitin Jindal ,  Rahul Mathur ,  Shruti Aggarwal ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/16 ,  G11C8/18 ,  G11C7/20

CPC classification number: G11C7/12 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

公开(公告)号：US20190267049A1

公开(公告)日：2019-08-29

申请号：US15904292

申请日：2018-02-23

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

IPC: G11C7/06 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

公开(公告)号：US10418124B1

公开(公告)日：2019-09-17

申请号：US15904292

申请日：2018-02-23

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Saikat Kumar Banik

IPC: G11C7/06 ,  G11C29/00 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12 ,  G11C29/56 ,  G11C29/28 ,  G11C16/04 ,  G11C29/12 ,  G11C29/14

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

公开(公告)号：US20190066769A1

公开(公告)日：2019-02-28

申请号：US15690562

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Nikhil Kaushik ,  Kapil Mittal ,  Divyank Gupta ,  Shakir Malik ,  Stefi Bhavsar

IPC: G11C11/418 ,  H01L27/11

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.

公开(公告)号：US10217506B1

公开(公告)日：2019-02-26

申请号：US15690562

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Vivek Asthana ,  Nitin Jindal ,  Nikhil Kaushik ,  Kapil Mittal ,  Divyank Gupta ,  Shakir Malik ,  Stefi Bhavsar

IPC: G11C11/418 ,  H01L27/11 ,  G11C11/419 ,  H01L21/8238

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.