公开(公告)号：US20190148398A1

公开(公告)日：2019-05-16

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L21/311

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：USD913980S1

公开(公告)日：2021-03-23

申请号：US29726623

申请日：2020-03-04

Applicant: ASM IP Holding B.V.

Designer： Hak Joo Lee ,  Jeong Jun Woo ,  Jong Hyun Ahn ,  Yoon Ki Min

公开(公告)号：US10734244B2

公开(公告)日：2020-08-04

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/3105

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：USD724553S1

公开(公告)日：2015-03-17

申请号：US29484673

申请日：2014-03-12

Applicant: ASM IP Holding B.V.

Designer： Seung Woo Choi ,  Hyung Wook Noh ,  Jeong Jun Woo ,  Dae Youn Kim ,  Hyun Soo Jang