公开(公告)号：US20190148398A1

公开(公告)日：2019-05-16

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L21/311

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：US10734244B2

公开(公告)日：2020-08-04

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/3105

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：US20180033625A1

公开(公告)日：2018-02-01

申请号：US15662107

申请日：2017-07-27

Applicant: ASM IP Holding B.V.

Inventor： Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3065

CPC classification number: H01L21/225 ,  H01L21/2255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31053

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

公开(公告)号：US20190081072A1

公开(公告)日：2019-03-14

申请号：US16188690

申请日：2018-11-13

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/115 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/1157

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20190035810A1

公开(公告)日：2019-01-31

申请号：US16147047

申请日：2018-09-28

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/115 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US10381226B2

公开(公告)日：2019-08-13

申请号：US15662107

申请日：2017-07-27

Applicant: ASM IP Holding B.V.

Inventor： Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

公开(公告)号：US10134757B2

公开(公告)日：2018-11-20

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20180130701A1

公开(公告)日：2018-05-10

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.