公开(公告)号：US10714335B2

公开(公告)日：2020-07-14

申请号：US15949990

申请日：2018-04-10

Applicant: ASM IP HOLDING B.V.

Inventor： Young Hoon Kim ,  Yong Gyu Han ,  Dae Youn Kim ,  Tae Hee Yoo ,  Wan Gyu Lim ,  Jin Geun Yu

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  C23C16/50 ,  C23C16/455 ,  C23C16/34

Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.

公开(公告)号：US10734244B2

公开(公告)日：2020-08-04

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/3105

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：US20180315758A1

公开(公告)日：2018-11-01

申请号：US15951644

申请日：2018-04-12

Applicant: ASM IP Holding B.V.

Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

IPC: H01L27/105 ,  H01L21/48 ,  H01L21/768 ,  H01L21/762 ,  G11C8/14

Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.

公开(公告)号：US20210035988A1

公开(公告)日：2021-02-04

申请号：US17072480

申请日：2020-10-16

Applicant: ASM IP Holding B.V.

Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

IPC: H01L27/1157 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11524 ,  H01L21/02 ,  H01L27/11575 ,  H01L27/11548

Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution,

公开(公告)号：US20190148398A1

公开(公告)日：2019-05-16

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L21/311

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：US20190115206A1

公开(公告)日：2019-04-18

申请号：US15949990

申请日：2018-04-10

Applicant: ASM IP HOLDING B.V.

Inventor： Young Hoon Kim ,  Yong Gyu Han ,  Dae Youn Kim ,  Tae Hee Yoo ,  Wan Gyu Lim ,  Jin Geun Yu

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  C23C16/50 ,  C23C16/455 ,  C23C16/34

Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.

公开(公告)号：US20180301460A1

公开(公告)日：2018-10-18

申请号：US15951626

申请日：2018-04-12

Applicant: ASM IP Holding B.V.

Inventor： Tae Hee Yoo ,  Yoon Ki Min ,  Yong Min Yoo

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311

Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.

公开(公告)号：US10950432B2

公开(公告)日：2021-03-16

申请号：US16897158

申请日：2020-06-09

Applicant: ASM IP HOLDING B.V.

Inventor： Young Hoon Kim ,  Yong Gyu Han ,  Dae Youn Kim ,  Tae Hee Yoo ,  Wan Gyu Lim ,  Jin Geun Yu

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  C23C16/50 ,  C23C16/455 ,  C23C16/34

Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.

公开(公告)号：US10134757B2

公开(公告)日：2018-11-20

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20180130701A1

公开(公告)日：2018-05-10

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.