公开(公告)号：US12045106B2

公开(公告)日：2024-07-23

申请号：US17564139

申请日：2021-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： Yinan Jiang

IPC: G06F1/24 ,  G06F9/455 ,  G06F11/14

CPC classification number: G06F1/24 ,  G06F9/45558 ,  G06F11/1484 ,  G06F2009/45575 ,  G06F2201/815

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

公开(公告)号：US20240211291A1

公开(公告)日：2024-06-27

申请号：US18088962

申请日：2022-12-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yuping Shen ,  Min Zhang ,  Yinan Jiang ,  Jeffrey G. Cheng

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A host processing system assigns unequal time slices at a parallel processor to virtual functions based on profiles of applications executing at the virtual functions and an available budget of the parallel processor. The host processing system calculates a world switch cycle interval and assesses an available processing budget of the parallel processor. The available budget indicates the amount of graphics processing time the parallel processor has not yet allocated to virtual functions for each world switch cycle interval.

公开(公告)号：US20240201876A1

公开(公告)日：2024-06-20

申请号：US18083306

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673

Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

公开(公告)号：US11182186B2

公开(公告)日：2021-11-23

申请号：US15663499

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Yinan Jiang ,  Andy Sung ,  Ahmed M. Abdelkhalek ,  Xiaowei Wang ,  Sidney D. Fortes

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48

Abstract: A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

公开(公告)号：US10509666B2

公开(公告)日：2019-12-17

申请号：US15637810

申请日：2017-06-29

Applicant: ATI Technologies ULC

Inventor： Anthony Asaro ,  Yinan Jiang ,  Kelly Donald Clark Zytaruk

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48 ,  G06F9/38 ,  G06F21/74 ,  G06F13/372 ,  G06F21/53

Abstract: A register protection mechanism for a virtualized accelerated processing device (“APD”) is disclosed. The mechanism protects registers of the accelerated processing device designated as physical-function-or-virtual-function registers (“PF-or-VF* registers”), which are single architectural instance registers that are shared among different functions that share the APD in a virtualization scheme whereby each function can maintain a different value in these registers. The protection mechanism for these registers comprises comparing the function associated with the memory address specified by a particular register access request to the “currently active” function for the APD and disallowing the register access request if a match does not occur.

公开(公告)号：US20190018699A1

公开(公告)日：2019-01-17

申请号：US15663499

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Yinan Jiang ,  Andy Sung ,  Ahmed M. Abdelkhalek ,  Xiaowei Wang ,  Sidney D. Fortes

IPC: G06F9/455 ,  G06F9/48

Abstract: A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

公开(公告)号：US20140380028A1

公开(公告)日：2014-12-25

申请号：US13923513

申请日：2013-06-21

Applicant: ATI Technologies ULC

Inventor： Gongxian Jeffrey CHENG ,  Anthony Asaro ,  Yinan Jiang

IPC: G06F9/455 ,  G06F1/24

CPC classification number: G06F9/45558 ,  G06F1/24 ,  G06F9/45533 ,  G06F11/1441 ,  G06F2009/4557 ,  G06F2009/45575 ,  G06F2009/45591

Abstract: In a hardware-based virtualization system, a hypervisor switches out of a first function into a second function. The first function is one of a physical function and a virtual function and the second function is one of a physical function and a virtual function. During the switching a malfunction of the first function is detected. The first function is reset without resetting the second function. The switching, detecting, and resetting operations are performed by a hypervisor of the hardware-based virtualization system. Embodiments further include a communication mechanism for the hypervisor to notify a driver of the function that was reset to enable the driver to restore the function without delay.

Abstract translation: 在基于硬件的虚拟化系统中，管理程序将第一个功能切换到第二个功能。 第一个功能是物理功能和虚拟功能之一，第二个功能是物理功能和虚拟功能之一。 在切换期间，检测到第一功能的故障。 第一个功能在不重置第二个功能的情况下被复位。 切换，检测和重置操作由基于硬件的虚拟化系统的管理程序执行。 实施例还包括用于管理程序的通信机制，以通知驾驶员已经重置的功能，以使得驾驶员能够无延迟地恢复功能。

公开(公告)号：US12265510B1

公开(公告)日：2025-04-01

申请号：US18478895

申请日：2023-09-29

Applicant: ATI Technologies ULC

Inventor： Yinan Jiang ,  Dmytro Chenchykov ,  Shaoyun Liu ,  Vignesh Chander

IPC: G06F16/00 ,  G06F16/21 ,  G06F21/64

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240211309A1

公开(公告)日：2024-06-27

申请号：US18085902

申请日：2022-12-21

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Ahmed M. Abdelkhalek ,  Rutao Zhang ,  Min Zhang ,  Yinan Jiang ,  Jeffrey G. Cheng ,  Yuping Shen ,  Mikhail Mironov

IPC: G06F9/48 ,  G06F9/455

CPC classification number: G06F9/4887 ,  G06F9/45558 ,  G06F2009/4557

Abstract: A parallel processor is configured to enforce job limits for virtual functions to facilitate an expected quality of service for each of the virtual functions assigned to a virtual machine executing at the processing unit. A scheduler schedules well-behaving virtual functions prior to badly-behaving virtual functions to prevent badly-behaving virtual functions from consuming a disproportionate share of hardware resources, thereby mitigating an impact of the badly-behaving virtual functions on the quality of service of the well-behaving virtual functions.

公开(公告)号：US20240211290A1

公开(公告)日：2024-06-27

申请号：US18088955

申请日：2022-12-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yuping Shen ,  Min Zhang ,  Yinan Jiang ,  Jeffrey G. Cheng

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545 ,  G06F2009/45579

Abstract: A processing system aligns rendering timing of an application executing at a guest virtual function to world switch timing of a host virtual machine. The host virtual machine sets a world switch interval based on a number of virtual functions (VFs) that share the parallel processor and a target maximum frame rate. The processing system delays submission of jobs for a VF to the parallel processor by an offset with respect to the world switch timing to ensure that the application starts generating a job for the parallel processor before the VF gains a time slice so the job will be ready for the parallel processor when the VF gains the time slice.