公开(公告)号：US10425053B2

公开(公告)日：2019-09-24

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32 ,  H03F1/02 ,  H03F1/30 ,  H03F3/187

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US20190207575A1

公开(公告)日：2019-07-04

申请号：US16295987

申请日：2019-03-07

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03F1/30 ,  H03F1/02 ,  H03G3/32 ,  H03F3/187

CPC classification number: H03G3/004 ,  H03F1/025 ,  H03F1/305 ,  H03F3/187 ,  H03F2200/507 ,  H03F2200/511 ,  H03G3/32

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US20190173484A1

公开(公告)日：2019-06-06

申请号：US16174118

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08 ,  H03M1/06

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US10230343B2

公开(公告)日：2019-03-12

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32 ,  H03F1/02 ,  H03F1/30 ,  H03F3/187

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US10158373B2

公开(公告)日：2018-12-18

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08 ,  H03M1/44 ,  H03M1/06

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US20180183458A1

公开(公告)日：2018-06-28

申请号：US15853779

申请日：2017-12-23

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/1033 ,  H03M1/188 ,  H03M1/447 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US20190173482A1

公开(公告)日：2019-06-06

申请号：US16173398

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/1033 ,  H03M1/188 ,  H03M1/447 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US10177779B2

公开(公告)日：2019-01-08

申请号：US15849227

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/44 ,  H03M1/06 ,  H03M1/08

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US20180183457A1

公开(公告)日：2018-06-28

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08

CPC classification number: H03M1/462 ,  H03M1/0678 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/442 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US20180183454A1

公开(公告)日：2018-06-28

申请号：US15832503

申请日：2017-12-05

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/06 ,  H03M1/14 ,  H03M1/80 ,  H03M1/16

CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/0695 ,  H03M1/124 ,  H03M1/145 ,  H03M1/164 ,  H03M1/181 ,  H03M1/468 ,  H03M1/806

Abstract: The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.