公开(公告)号：US20220318161A1

公开(公告)日：2022-10-06

申请号：US17219273

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Indrani Paul ,  Jean J. Chittilappilly ,  Abhishek Kumar Verma ,  James R. Magro ,  Kavyashree Pilar

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/406

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

公开(公告)号：US11934251B2

公开(公告)日：2024-03-19

申请号：US17219407

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Christopher Weaver ,  Abhishek Kumar Verma

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F3/06

CPC classification number: G06F1/3275 ,  G06F1/08 ,  G06F1/3225 ,  G06F1/3287 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

公开(公告)号：US11636054B2

公开(公告)日：2023-04-25

申请号：US17219273

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Indrani Paul ,  Jean J. Chittilappilly ,  Abhishek Kumar Verma ,  James R. Magro ,  Kavyashree Pilar

IPC: G06F1/3234 ,  G06F13/16 ,  G11C11/406 ,  G06F1/3296 ,  G06F3/06

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

公开(公告)号：US20220317755A1

公开(公告)日：2022-10-06

申请号：US17219407

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Christopher Weaver ,  Abhishek Kumar Verma

IPC: G06F1/3234 ,  G06F1/3225 ,  G06F1/3287 ,  G06F1/08 ,  G06F3/06

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.