公开(公告)号：US20250044966A1

公开(公告)日：2025-02-06

申请号：US18362796

申请日：2023-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Nicholas Carmine DeFiore ,  Sridhar Varadharajulu Gada ,  James R. Magro ,  Michael L. Choate ,  Wayne Paul Rodrigue ,  NrusimhaVamsi Krishna Godavarti ,  Robert Gentile ,  Roozbeh Paribakht ,  Anwar Kashem

IPC: G06F3/06

Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12141038B2

公开(公告)日：2024-11-12

申请号：US18084350

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/14 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

公开(公告)号：US20240220379A1

公开(公告)日：2024-07-04

申请号：US18091163

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/2094 ,  G06F11/1402 ,  G06F2201/805

Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.

公开(公告)号：US20220405214A1

公开(公告)日：2022-12-22

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20210382661A1

公开(公告)日：2021-12-09

申请号：US17409099

申请日：2021-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.

公开(公告)号：US10037150B2

公开(公告)日：2018-07-31

申请号：US15252889

申请日：2016-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0674 ,  G06F13/287 ,  G06F13/4022 ,  G11C7/1072

Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.

公开(公告)号：US09965222B1

公开(公告)日：2018-05-08

申请号：US15299994

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Scott P. Murphy ,  James R. Magro ,  Paramjit K. Lubana

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F13/16

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

公开(公告)号：US20180019006A1

公开(公告)日：2018-01-18

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G11C11/408

CPC classification number: G11C7/1063 ,  G06F12/1018 ,  G06F2212/1041 ,  G11C7/10 ,  G11C7/1072 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US20180018221A1

公开(公告)日：2018-01-18

申请号：US15375076

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

IPC: G06F11/10 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

公开(公告)号：US20180018105A1

公开(公告)日：2018-01-18

申请号：US15252889

申请日：2016-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0674 ,  G06F13/287 ,  G06F13/4022 ,  G11C7/1072

Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.