公开(公告)号：US11275688B2

公开(公告)日：2022-03-15

申请号：US16700671

申请日：2019-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US20210152432A1

公开(公告)日：2021-05-20

申请号：US16688814

申请日：2019-11-19

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Kartik Shenoy

IPC: H04L12/24 ,  H04L12/26

Abstract: A communication network includes: a plurality of nodes in a topology, with each node having an upstream and a downstream neighboring node in the topology; a separate unidirectional communication link coupled between each node and that node's downstream neighboring node; and a separate unidirectional control link coupled between each node and that node's upstream neighboring node. A controller in each node keeps a count of packets sent by that node via the corresponding unidirectional communication link. The controller uses the count of packets sent to determine whether a given packet is allowed to be sent from that node to the downstream neighboring node and, if so, whether a full rate or a throttled rate is to be used for sending the given packet. Based at least in part on the determining, the controller selectively sends the given packet to the downstream neighboring node.

公开(公告)号：US11803473B2

公开(公告)日：2023-10-31

申请号：US17521483

申请日：2021-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

公开(公告)号：US11693778B2

公开(公告)日：2023-07-04

申请号：US17118612

申请日：2020-12-11

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley

IPC: G06F12/084 ,  G06F11/30 ,  G06F12/126 ,  G06F12/128

CPC classification number: G06F12/084 ,  G06F11/3037 ,  G06F12/126 ,  G06F12/128

Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.

公开(公告)号：US11467937B2

公开(公告)日：2022-10-11

申请号：US17004589

申请日：2020-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F11/30 ,  G06F11/34 ,  G06F12/0804 ,  G06F12/0891 ,  G06F11/07

Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.

公开(公告)号：US09910638B1

公开(公告)日：2018-03-06

申请号：US15247416

申请日：2016-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Hanbing Liu ,  John Kelley ,  Michael Estlick ,  Erik Swanson ,  Jay Fleischman

IPC: G06F7/38 ,  G06F7/552 ,  G06F7/535

CPC classification number: G06F7/5525 ,  G06F7/535 ,  G06F2207/5523

Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.

公开(公告)号：US20180060039A1

公开(公告)日：2018-03-01

申请号：US15247416

申请日：2016-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Hanbing Liu ,  John Kelley ,  Michael Estlick ,  Erik Swanson ,  Jay Fleischman

IPC: G06F7/552 ,  G06F7/535

CPC classification number: G06F7/5525 ,  G06F7/535 ,  G06F2207/5523

Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.

公开(公告)号：US11928060B2

公开(公告)日：2024-03-12

申请号：US17666950

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram Srinivasan ,  John Kelley ,  Matthew Schoenwald

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/1021 ,  G06F2212/1041

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US11868221B2

公开(公告)日：2024-01-09

申请号：US17490862

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Vanchinathan Venkataramani ,  Paul J. Moyer

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/263 ,  G06F11/076 ,  G06F11/3037 ,  G06F11/3409 ,  G06F11/3457

Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.

公开(公告)号：US20230289290A1

公开(公告)日：2023-09-14

申请号：US18319016

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley

IPC: G06F12/084 ,  G06F11/30 ,  G06F12/126 ,  G06F12/128

CPC classification number: G06F12/084 ,  G06F11/3037 ,  G06F12/126 ,  G06F12/128

Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.