-
公开(公告)号：US10129011B2
公开(公告)日：2018-11-13
申请号：US15605082
申请日：2017-05-25
Applicant: Analog Devices Global
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
-
2.发明授权Apparatus and method for evaluating the performance of a system in a control loop 有权用于评估控制回路中系统性能的装置和方法公开(公告)号：US09594100B2
公开(公告)日：2017-03-14
申请号：US14020404
申请日：2013-09-06
Applicant: ANALOG DEVICES GLOBAL
Inventor： Muhammad Kalimuddin Khan , Kenneth J. Mulvaney , Michael Deeney , Niall Kevin Kearney
CPC classification number: G01R23/02 , H03L7/095 , H03L7/193 , H03L7/1974 , H03L7/1976
Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.
Abstract translation: 一种用于监视其中具有分频器的锁相环的性能的监视电路，所述分频器包括至少第一计数器，所述分频器包括至少一个存储器元件，用于在来自系统的预定时间之后捕获所述第一计数器的值 可变性计算器，用于将计数器的值与计数器的先前值进行比较以计算变化;以及电路，其响应于用于输出状态信号的变化估计。
-
公开(公告)号：US09673962B1
公开(公告)日：2017-06-06
申请号：US15045826
申请日：2016-02-17
Applicant: Analog Devices Global
CPC classification number: H04L7/0008 , H04L7/033 , H04L7/0331 , H04L7/046
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
-
公开(公告)号：US20150365118A1
公开(公告)日：2015-12-17
申请号：US14302223
申请日：2014-06-11
Applicant: ANALOG DEVICES GLOBAL
Inventor： Muhammad Kalimuddin Khan , Michael J. Deeney , Niall Kevin Kearney , Kenneth J. Mulvaney , Shane A. O'Mahony
CPC classification number: H03G3/3052 , H03G3/3068 , H04B1/30 , H04B2001/305
Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.
Abstract translation: LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC RF信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。
-
公开(公告)号：US20150270948A1
公开(公告)日：2015-09-24
申请号：US14218697
申请日：2014-03-18
Applicant: ANALOG DEVICES GLOBAL
Inventor： Muhammad Kalimuddin Khan , Philip Quinlan , Kenneth J. Mulvaney
CPC classification number: H04L7/0331 , H03L7/07 , H03L7/0807 , H04L7/0016 , H04L7/046 , H04L7/10
Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.
Abstract translation: 公开了用于时钟和数据恢复的装置和方法。 复位电路对输入信号的边沿之间的时钟周期进行计数，并且当时钟周期计数超出范围时，复位执行数据流的采集和跟踪的信号处理电路。 信号处理电路还被配置为根据校正的数据速率执行采集和跟踪，该数据速率可以通过相位误差校正控制环路的数据速率调整和/或两个数据速率之间的抖动来产生。
-
Patent Agency Ranking
公开(公告)号：US20170264422A1
公开(公告)日：2017-09-14
申请号：US15605082
申请日：2017-05-25
Applicant: Analog Devices Global
Inventor： Muhammad Kalimuddin Khan , Kenneth J. Mulvaney , Philip P.E. Quinlan , Shane O'Mahony
CPC classification number: H04L7/0008 , H04L7/033 , H04L7/0331 , H04L7/046
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
-
公开(公告)号：US09749125B2
公开(公告)日：2017-08-29
申请号：US14568818
申请日：2014-12-12
Applicant: Analog Devices Global
Inventor： Muhammad Kalimuddin Khan , Kenneth J. Mulvaney
Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.
-
公开(公告)号：US09553717B2
公开(公告)日：2017-01-24
申请号：US14218697
申请日：2014-03-18
Applicant: ANALOG DEVICES GLOBAL
Inventor： Muhammad Kalimuddin Khan , Philip Quinlan , Kenneth J. Mulvaney
CPC classification number: H04L7/0331 , H03L7/07 , H03L7/0807 , H04L7/0016 , H04L7/046 , H04L7/10
Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.
Abstract translation: 公开了用于时钟和数据恢复的装置和方法。 复位电路对输入信号的边沿之间的时钟周期进行计数，并且当时钟周期计数超出范围时，复位执行数据流的采集和跟踪的信号处理电路。 信号处理电路还被配置为根据校正的数据速率执行采集和跟踪，该数据速率可以通过相位误差校正控制环路的数据速率调整和/或两个数据速率之间的抖动来产生。
-
公开(公告)号：US09391578B2
公开(公告)日：2016-07-12
申请号：US14302223
申请日：2014-06-11
Applicant: ANALOG DEVICES GLOBAL
Inventor： Muhammad Kalimuddin Khan , Michael J. Deeney , Niall Kevin Kearney , Kenneth J. Mulvaney , Shane A. O'Mahony
CPC classification number: H03G3/3052 , H03G3/3068 , H04B1/30 , H04B2001/305
Abstract: An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.
Abstract translation: LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC 射频信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。
-
公开(公告)号：US20160173272A1
公开(公告)日：2016-06-16
申请号：US14568818
申请日：2014-12-12
Applicant: Analog Devices Global
Inventor： Muhammad Kalimuddin Khan , Kenneth J. Mulvaney
IPC: H04L7/04
Abstract: A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.
Abstract translation: 时钟和数据恢复（CDR）系统可以使用与恢复的数据速率同步的一个或多个时钟信号。 通过以数据过采样率累积抖动调谐计数器值，可以在利用累加器的全范围的同时，以恢复的数据速率的倍数与恢复的数据速率同步的多个单比特信号被精确地产生。 该多个时钟信号可以用在CDR系统中的各种模块中以及包含CDR系统的收发机系统中的其他模块中。
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.016 seconds)
