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公开(公告)号：US10680624B2
公开(公告)日：2020-06-09
申请号：US16129599
申请日：2018-09-12
摘要： This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.
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公开(公告)号：US20170155414A1
公开(公告)日：2017-06-01
申请号：US14956257
申请日：2015-12-01
CPC分类号： H04B1/126 , H03F1/0205 , H03F1/301 , H03F3/193 , H03F3/45179 , H03F2200/294 , H03F2200/451
摘要： Provided herein are apparatus and methods for transconductance amplifiers, such as split cascode low-noise transconductance amplifiers (LNTAs). In an embodiment, an LNTA includes split current paths each coupled to a different mixer by way of a different alternating current (AC) coupling capacitor. The split current paths of the LNTA can be enabled during different modes of operation, such as when the input to the LNTA is within different frequency bands.
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3.发明授权Delta-sigma modulator having transconductor network for dynamically tuning loop filter coefficients 有权具有用于动态调整环路滤波器系数的跨导网络的Δ-Σ调制器公开(公告)号：US09590590B2
公开(公告)日：2017-03-07
申请号：US14537836
申请日：2014-11-10
CPC分类号： H03H11/0422 , H03M3/396 , H03M3/422 , H03M3/438 , H03M3/458
摘要： A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.
摘要翻译： 一种动态可调谐的跨导体包括用于基于电压信号产生电流信号的电压 - 电流转换器级; 以及用于按比例因子缩放当前信号以实现特定跨导的电流缩放级。 当前缩放级包括具有相关联的粗调步骤的粗调机构和具有相关联的微调步骤的微调机构，其中缩放因子是粗调步骤与微调步骤的比率。 Δ-Σ调制器可以通过动态调谐跨导来实现跨导体来产生环路滤波器系数以实现特定的电阻。
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公开(公告)号：US20190280698A1
公开(公告)日：2019-09-12
申请号：US16129599
申请日：2018-09-12
摘要： This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.
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公开(公告)号：US20150365118A1
公开(公告)日：2015-12-17
申请号：US14302223
申请日：2014-06-11
发明人： Muhammad Kalimuddin Khan , Michael J. Deeney , Niall Kevin Kearney , Kenneth J. Mulvaney , Shane A. O'Mahony
CPC分类号： H03G3/3052 , H03G3/3068 , H04B1/30 , H04B2001/305
摘要： An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.
摘要翻译： LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC RF信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。
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公开(公告)号：US09755678B2
公开(公告)日：2017-09-05
申请号：US14956257
申请日：2015-12-01
CPC分类号： H04B1/126 , H03F1/0205 , H03F1/301 , H03F3/193 , H03F3/45179 , H03F2200/294 , H03F2200/451
摘要： Provided herein are apparatus and methods for transconductance amplifiers, such as split cascode low-noise transconductance amplifiers (LNTAs). In an embodiment, an LNTA includes split current paths each coupled to a different mixer by way of a different alternating current (AC) coupling capacitor. The split current paths of the LNTA can be enabled during different modes of operation, such as when the input to the LNTA is within different frequency bands.
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7.发明授权Apparatus and method for evaluating the performance of a system in a control loop 有权用于评估控制回路中系统性能的装置和方法公开(公告)号：US09594100B2
公开(公告)日：2017-03-14
申请号：US14020404
申请日：2013-09-06
CPC分类号： G01R23/02 , H03L7/095 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.
摘要翻译： 一种用于监视其中具有分频器的锁相环的性能的监视电路，所述分频器包括至少第一计数器，所述分频器包括至少一个存储器元件，用于在来自系统的预定时间之后捕获所述第一计数器的值 可变性计算器，用于将计数器的值与计数器的先前值进行比较以计算变化;以及电路，其响应于用于输出状态信号的变化估计。
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公开(公告)号：US09391578B2
公开(公告)日：2016-07-12
申请号：US14302223
申请日：2014-06-11
发明人： Muhammad Kalimuddin Khan , Michael J. Deeney , Niall Kevin Kearney , Kenneth J. Mulvaney , Shane A. O'Mahony
CPC分类号： H03G3/3052 , H03G3/3068 , H04B1/30 , H04B2001/305
摘要： An LIF receiver includes a receiver path comprising: a mixer for mixing a received RF signal with a local oscillator signal to provide an IF signal at a lower frequency than the received RF signal, a bandpass filter for filtering the IF signal, a PGA for amplifying the filtered IF signal, an ADC for converting the amplified filtered IF signal to a digital signal, a converter for converting the digital signal to a baseband digital signal, and an AGC for setting a gain of the PGA in response to a magnitude of the received RF signal. A programmable DC signal source injects a programmed DC offset signal into the amplified filtered IF signal converted by the ADC, and a signal sensor, operatively connected to the receiver path after the PGA, determines a polarity of PGA signal output for a programmed DC offset signal. A controller determines a programmed DC offset signal minimizing a magnitude of the baseband signal in the absence of a received RF signal for at least one gain setting of the PGA.
摘要翻译： LIF接收机包括：接收机路径，包括：混合器，用于将接收到的RF信号与本地振荡器信号混合，以提供比所接收的RF信号低的频率的IF信号;滤波IF信号的带通滤波器;用于放大的PGA 经滤波的IF信号，用于将放大的滤波IF信号转换为数字信号的ADC，用于将数字信号转换为基带数字信号的转换器，以及响应于接收到的幅度的设定PGA的增益的AGC 射频信号。 可编程DC信号源将经编程的DC偏移信号注入由ADC转换的经放大的经滤波的IF信号中，并且在PGA之后可操作地连接到接收器路径的信号传感器确定编程的DC偏移信号的PGA信号输出的极性 。 控制器确定在没有接收的RF信号的情况下使PGA的至少一个增益设置最小化基带信号幅度的编程的DC偏移信号。
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公开(公告)号：US09160356B1
公开(公告)日：2015-10-13
申请号：US14334545
申请日：2014-07-17
IPC分类号： H03M1/10
摘要： An analog to digital convertor (ADC) comprises an integrator having an input selectively connected to an intermediate frequency (IF) signal input and an output connected to a summer. The summer has an output connected to an input of a quantizer, the quantizer output being operatively connected to a signal strength indicator. The integrator includes a programmable gain feedback component. The summer has a synthesized calibration signal input, the value of the programmable gain feedback component being configured to vary when a synthesized calibration signal at the intermediate frequency is applied to the summer. The signal strength indicator is configured to detect a value of the programmable gain feedback component when the signal strength is minimized and to calibrate the ADC accordingly.
摘要翻译： 模数转换器（ADC）包括积分器，其具有选择性地连接到中频（IF）信号输入的输入端和连接到夏季的输出。 夏季具有连接到量化器的输入的输出，量化器输出可操作地连接到信号强度指示器。 积分器包括可编程增益反馈分量。 夏季具有合成的校准信号输入，可编程增益反馈分量的值被配置为当将中频处的合成校准信号施加到夏季时变化。 信号强度指示器被配置为当信号强度最小化时检测可编程增益反馈分量的值，并相应地校准ADC。
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