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    Programmable logic array integrated circuits
    4.
    发明授权
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：US5828229A

    公开(公告)日：1998-10-27

    申请号：US847004

    申请日：1997-05-01

    申请人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    发明人： Richard G. Cliff ,  L. Todd Cope ,  Cameron McClintock ,  William Leong ,  James Allen Watson ,  Joseph Huang ,  Bahram Ahanin ,  Chiakang Sung ,  Wanli Chang

    IPC分类号： G01R31/3185 ,  G11C8/12 ,  G11C8/16 ,  G11C29/32 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  G11C29/32 ,  G11C8/12 ,  G11C8/16 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/17764 ,  G01R31/318516

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。 随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。 此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

    Redundancy circuitry for logic circuits
    8.
    发明授权
    Redundancy circuitry for logic circuits 有权
    用于逻辑电路的冗余电路

    公开(公告)号：US6091258A

    公开(公告)日：2000-07-18

    申请号：US433544

    申请日：1999-11-03

    申请人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    发明人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    IPC分类号： G06F11/20 ,  G11C29/00 ,  H03K19/177 ,  H03K19/003 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G11C29/808 ,  H03K19/17728

    摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

    摘要翻译： 提供了诸如可编程逻辑器件之类的逻辑电路的冗余电路。 冗余电路允许通过用冗余逻辑电路替换电路上的故障逻辑区域来修复逻辑电路。 逻辑区域的行和列可以通过行和列交换逻辑地重新映射。 逻辑电路包含动态控制电路，用于以由冗余配置数据定义的顺序将编程数据引导到电路上的各种逻辑区域。 可以使用完全或部分冗余的逻辑区域实现冗余。 可以交换逻辑区域以将部分冗余的逻辑区域重新映射到包含缺陷的逻辑区域。 然后可以使用行或列交换或移位来修复缺陷。 可以通过用冗余半行代替缺陷半行来修复包含折叠行的逻辑区域的逻辑电路。

    Redundancy circuitry for logic circuits
    9.
    发明授权
    Redundancy circuitry for logic circuits 失效

    公开(公告)号：US6034536A

    公开(公告)日：2000-03-07

    申请号：US982297

    申请日：1997-12-01

    申请人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    发明人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    IPC分类号： G06F11/20 ,  G11C29/00 ,  H03K19/177 ,  H03K19/003 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G11C29/808 ,  H03K19/17728 ,  H03K19/17736

    摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

    Programmable logic device with enhanced multiplexing capabilities in interconnect resources
    10.
    发明授权
    Programmable logic device with enhanced multiplexing capabilities in interconnect resources 有权
    具有增强的互连资源复用能力的可编程逻辑器件

    公开(公告)号：US06278288B1

    公开(公告)日：2001-08-21

    申请号：US09574371

    申请日：2000-05-19

    申请人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    发明人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    IPC分类号： G06F738

    CPC分类号： H03K19/17752 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1778

    摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.

    摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。