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    Traffic isolation at a chip-to-chip gateway of a data processing system
    1.
    发明授权
    Traffic isolation at a chip-to-chip gateway of a data processing system 有权

    公开(公告)号：US12222826B2

    公开(公告)日：2025-02-11

    申请号：US18104458

    申请日：2023-02-01

    Applicant: Arm Limited

    Inventor： Ashok Kumar Tummala ,  FNU Parshant ,  Rishabh Jain ,  Apurva Patel ,  Surabhi Garg ,  Sai Kumar Marri

    IPC: G06F11/07 ,  G06F11/20

    Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

    Method and Apparatus for Efficient Chip-To-Chip Data Transfer
    3.
    发明公开
    Method and Apparatus for Efficient Chip-To-Chip Data Transfer 审中-公开

    公开(公告)号：US20240256460A1

    公开(公告)日：2024-08-01

    申请号：US18101806

    申请日：2023-01-26

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Ashok Kumar Tummala ,  Wenxuan Zhang ,  Daniel Thomas Pinero ,  Tushar P Ringe

    IPC: G06F12/0888

    CPC classification number: G06F12/0888 ,  G06F2212/1024

    Abstract: Efficient data transfer between caching domains of a data processing system is achieved by a local coherency node (LCN) of a first caching domain receiving a read request for data associated with a second caching domain, from a requesting node of the first caching domain. The LCN requests the data from the second caching domain via a transfer agent. In response to receiving a cache line containing the data from the second caching domain, the transfer agent sends the cache line to the requesting node, bypassing the LCN and, optionally, sends a read-receipt indicating the state of the cache line to the LCN. The LCN updates a coherency state for the cache line in response to receiving the read-receipt from the transfer agent and a completion acknowledgement from the requesting node. Optionally, the transfer agent may send the cache line via the LCN when congestion is detected in a response channel of the data processing system.

    Method and apparatus for efficient chip-to-chip data transfer
    6.
    发明授权
    Method and apparatus for efficient chip-to-chip data transfer 有权

    公开(公告)号：US12079132B2

    公开(公告)日：2024-09-03

    申请号：US18101806

    申请日：2023-01-26

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Ashok Kumar Tummala ,  Wenxuan Zhang ,  Daniel Thomas Pinero ,  Tushar P Ringe

    IPC: G06F12/00 ,  G06F12/0888

    CPC classification number: G06F12/0888 ,  G06F2212/1024

    Abstract: Data transfer between caching domains of a data processing system is achieved by a local coherency node (LCN) of a first caching domain receiving a read request for data associated with a second caching domain, from a requesting node of the first caching domain. The LCN requests the data from the second caching domain via a transfer agent. In response to receiving a cache line containing the data from the second caching domain, the transfer agent sends the cache line to the requesting node, bypassing the LCN and, optionally, sends a read-receipt indicating the state of the cache line to the LCN. The LCN updates a coherency state for the cache line in response to receiving the read-receipt from the transfer agent and a completion acknowledgement from the requesting node. Optionally, the transfer agent may send the cache line via the LCN when congestion is detected in a response channel of the data processing system.

    Apparatus and method for handling ordered transactions
    7.
    发明授权
    Apparatus and method for handling ordered transactions 有权

    公开(公告)号：US11256646B2

    公开(公告)日：2022-02-22

    申请号：US16685082

    申请日：2019-11-15

    Applicant: Arm Limited

    Inventor： Tushar P Ringe ,  Jamshed Jalal ,  Gurunath Ramagiri ,  Ashok Kumar Tummala ,  Mark David Werkheiser

    IPC: G06F13/40 ,  G06F9/46

    Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

    Message protocol for a data processing system
    8.
    发明授权
    Message protocol for a data processing system 有权

    公开(公告)号：US11074206B1

    公开(公告)日：2021-07-27

    申请号：US17036225

    申请日：2020-09-29

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  Ashok Kumar Tummala ,  Rishabh Jain ,  Devi Sravanthi Yalamarthy

    IPC: G06F13/28 ,  G06F13/40 ,  G06F9/46

    Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

    High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs
    9.
    发明授权
    High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs 有权

    公开(公告)号：US10452593B1

    公开(公告)日：2019-10-22

    申请号：US16027490

    申请日：2018-07-05

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Tushar P. Ringe ,  Ashok Kumar Tummala ,  Gurunath Ramagiri

    IPC: G06F13/42 ,  G06F12/0831 ,  G06F15/173

    Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

    Traffic Isolation at a Chip-To-Chip Gateway of a Data Processing System
    10.
    发明公开
    Traffic Isolation at a Chip-To-Chip Gateway of a Data Processing System 审中-公开

    公开(公告)号：US20240256406A1

    公开(公告)日：2024-08-01

    申请号：US18104458

    申请日：2023-02-01

    Applicant: Arm Limited

    Inventor： Ashok Kumar Tummala ,  FNU Parshant ,  Rishabh Jain ,  Apurva Patel ,  Surabhi Garg ,  Sai Kumar Marri

    IPC: G06F11/20

    CPC classification number: G06F11/2007 ,  G06F11/203 ,  G06F2201/805

    Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

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