公开(公告)号：US08889532B2

公开(公告)日：2014-11-18

申请号：US13170033

申请日：2011-06-27

申请人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/36 ,  H01L21/20 ,  H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L29/45 ,  H01L29/417 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7827

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括形成在半导体材料内的沟槽结构中的屏蔽电极。 栅电极使用栅极绝缘层与半导体材料隔离。 在形成屏蔽电极之前，间隔层可以沿沟槽结构的部分形成屏蔽绝缘层。 屏蔽绝缘层比栅极绝缘层厚。 在另一个实施例中，屏蔽绝缘层具有可变的厚度。

公开(公告)号：US20130248982A1

公开(公告)日：2013-09-26

申请号：US13895197

申请日：2013-05-15

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

公开(公告)号：US09466708B2

公开(公告)日：2016-10-11

申请号：US13831883

申请日：2013-03-15

申请人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

发明人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/70 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/66666 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

摘要翻译： 在一个实施例中，半导体器件形成为包括延伸到半导体材料中的栅极结构，该半导体材料位于半导体材料的第一区域下方。 栅极结构包括导体和栅极绝缘体，栅极绝缘体具有位于栅极导体与栅极导体之下的半导体材料的第一部分之间的第一部分。 半导体材料的第一部分被配置为形成在栅极导体下面的晶体管的沟道区。 栅极结构还可以包括覆盖栅极导体并且在屏蔽导体和栅极导体之间​​具有屏蔽绝缘体的屏蔽导体。 屏蔽绝缘体还可以具有位于屏蔽导体和栅极绝缘体的第二部分之间的第二部分和覆盖屏蔽导体的第三部分。

公开(公告)号：US08878286B2

公开(公告)日：2014-11-04

申请号：US13895197

申请日：2013-05-15

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括嵌入在控制电极内的特征。 该特征被放置在控制电极内以在晶体管的预定区域内引起应力。

公开(公告)号：US20120313161A1

公开(公告)日：2012-12-13

申请号：US13159255

申请日：2011-06-13

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括嵌入在控制电极内的特征。 该特征被放置在控制电极内以在晶体管的预定区域内引起应力。

公开(公告)号：US09029215B2

公开(公告)日：2015-05-12

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。

公开(公告)号：US20140264565A1

公开(公告)日：2014-09-18

申请号：US13831883

申请日：2013-03-15

申请人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

发明人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66666 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7834 ,  H01L29/7835

摘要： In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

摘要翻译： 在一个实施例中，半导体器件形成为包括延伸到半导体材料中的栅极结构，该半导体材料位于半导体材料的第一区域下方。 栅极结构包括导体和栅极绝缘体，栅极绝缘体具有位于栅极导体与栅极导体之下的半导体材料的第一部分之间的第一部分。 半导体材料的第一部分被配置为形成在栅极导体下面的晶体管的沟道区。 栅极结构还可以包括覆盖栅极导体并且在屏蔽导体和栅极导体之间​​具有屏蔽绝缘体的屏蔽导体。 屏蔽绝缘体还可以具有位于屏蔽导体和栅极绝缘体的第二部分之间的第二部分和覆盖屏蔽导体的第三部分。

公开(公告)号：US08723238B1

公开(公告)日：2014-05-13

申请号：US13831887

申请日：2013-03-15

申请人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

发明人： Balaji Padmanabhan ,  Prasad Venkatraman ,  Gordon M. Grivna

IPC分类号： H01L29/76

CPC分类号： H01L29/407 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834

摘要： In one embodiment, a semiconductor device is formed to include a gate structure extending into a first portion of a semiconductor material that is underlying a first region of semiconductor material. The gate structure separates a portion of the first region into at least a first current carrying electrode region and a second current carrying electrode region. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies a gate conductor of the gate structure. The gate structure also includes a shield conductor overlying the gate conductor and having a shield insulator positioned between the shield conductor and the gate conductor. The shield insulator also having a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

摘要翻译： 在一个实施例中，半导体器件被形成为包括延伸到半导体材料的第一部分的栅极结构，其位于半导体材料的第一区域下方。 栅极结构将第一区域的一部分分成至少第一载流电极区域和第二载流电极区域。 半导体材料的第一部分被配置为形成在栅极结构的栅极导体下面的晶体管的沟道区。 栅极结构还包括覆盖栅极导体并具有位于屏蔽导体和栅极导体之间​​的屏蔽绝缘体的屏蔽导体。 屏蔽绝缘体还具有位于屏蔽导体和栅极绝缘体的第二部分之间的第二部分和覆盖屏蔽导体的第三部分。

公开(公告)号：US20120326227A1

公开(公告)日：2012-12-27

申请号：US13170033

申请日：2011-06-27

申请人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Peter A. Burke ,  Gordon M. Grivna ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7827

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括形成在半导体材料内的沟槽结构中的屏蔽电极。 栅电极使用栅极绝缘层与半导体材料隔离。 在形成屏蔽电极之前，间隔层可以沿沟槽结构的部分形成屏蔽绝缘层。 屏蔽绝缘层比栅极绝缘层厚。 在另一个实施例中，屏蔽绝缘层具有可变的厚度。

公开(公告)号：US20130302958A1

公开(公告)日：2013-11-14

申请号：US13471105

申请日：2012-05-14

申请人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

发明人： Zia Hossain ,  Gordon M. Grivna ,  Duane B. Barber ,  Peter McGrath ,  Balaji Padmanabhan ,  Prasad Venkatraman

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

摘要翻译： 在一个实施例中，形成半导体器件的方法包括沿着沟槽的表面形成沟槽和电介质层。 屏蔽电极形成在沟槽的下部，电介质层从沟槽的上侧壁表面去除。 栅极电介质层沿沟槽的上表面形成。 沿着栅极电介质层形成耐氧化间隔物。 此后，使用局部氧化在屏蔽电极上方形成间隔电介质层。 氧化步骤增加了栅极电介质层的下部的厚度。 在形成邻近栅极电介质层的栅电极之前去除抗氧化间隔物。