公开(公告)号：US06944041B1

公开(公告)日：2005-09-13

申请号：US10811454

申请日：2004-03-26

Applicant: Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

Inventor： Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

IPC: G11C11/00 ,  G11C13/00 ,  G11C16/02 ,  G11C16/34

CPC classification number: G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069

Abstract: A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.

Abstract translation: 公开了一种用于访问硫族化物存储器阵列的电路。 硫族化物存储器阵列包括具有由硫族化物存储元件形成的行和列的多个子阵列。 硫族化物存储器阵列由离散读和写电路访问。 与相应的一个子阵列相关联，每个写入电路包括独立的写入0电路和独立的写入1电路。 还与相应的一个子阵列相关联，每个读取电路包括读出放大器电路。 此外，电压电平控制模块耦合到读取和写入电路，以确保在读取和写入操作期间跨硫族化物存储器阵列内的硫族化物存储元件的电压不超过预定值。

公开(公告)号：US06327176B1

公开(公告)日：2001-12-04

申请号：US09844079

申请日：2001-04-26

Applicant: Bin Li ,  David C. Lawson

Inventor： Bin Li ,  David C. Lawson

IPC: G11C11412

CPC classification number: G11C11/4125

Abstract: A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

Abstract translation: 公开了一种单件事件硬化锁定电路。 单事件硬化锁存电路包括第一双端口反相器和第二双端口反相器。 输入端通过第一组通道门耦合到第一双端口逆变器。 第一个双端口逆变器通过第二组通孔连接到第二个双端口逆变器。 输出端连接到第一和第二双端口逆变器。

公开(公告)号：US07099187B2

公开(公告)日：2006-08-29

申请号：US11225953

申请日：2005-09-14

Applicant: Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

Inventor： Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/004

Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

公开(公告)号：US06965521B2

公开(公告)日：2005-11-15

申请号：US10631174

申请日：2003-07-31

Applicant: Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

Inventor： Bin Li ,  Kenneth R. Knowles ,  David C. Lawson

IPC: G11C11/00 ,  G11C16/02 ,  G11C16/26

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/004

Abstract: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

公开(公告)号：US06215694B1

公开(公告)日：2001-04-10

申请号：US09553595

申请日：2000-04-20

Applicant: Bin Li ,  Livia L. Zien ,  David C. Lawson ,  Tatia B. Butts ,  Tri M. Hoang

Inventor： Bin Li ,  Livia L. Zien ,  David C. Lawson ,  Tatia B. Butts ,  Tri M. Hoang

IPC: G11C1100

CPC classification number: G11C11/4125

Abstract: A single event upset hardened multiport memory cell to be utilized in a register file is disclosed. The single event upset hardened multiport memory cell includes a storage cell, a write bitline, a read bitline. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.

Abstract translation: 公开了一种用于寄存器文件中的单事件硬化多端口存储单元。 单事件硬化多端口存储单元包括存储单元，写位线，读位线。 用于存储数据的存储单元包括第一组和第二组交叉耦合晶体管和第一组和第二组隔离晶体管。 第一和第二组隔离晶体管分别耦合到第一和第二组交叉耦合晶体管，使得在两组交叉耦合晶体管和两组隔离晶体管之间形成两个反转路径。 耦合到存储单元，写位线输入将数据写入存储单元。 读取位线也耦合到存储单元，从存储单元输出读取数据。

公开(公告)号：US08411490B2

公开(公告)日：2013-04-02

申请号：US10890430

申请日：2004-07-10

Applicant: David C. Lawson ,  Edward Maher ,  Shankarnarayana Ramaswamy ,  Tri Minh Hoang

Inventor： David C. Lawson ,  Edward Maher ,  Shankarnarayana Ramaswamy ,  Tri Minh Hoang

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: A sense amplifier for static random access memories is disclosed. The sense amplifier includes a pair of inverters cross-coupled to each other. The sense amplifier also includes means for equalizing the charges within the pair of inverters before performing a sense operation, and means for sensing a current difference between a bitline and its complement from a memory cell during the sense operation.

Abstract translation: 公开了一种用于静态随机存取存储器的读出放大器。 读出放大器包括彼此交叉耦合的一对反相器。 感测放大器还包括用于在执行感测操作之前均衡一对逆变器中的电荷的装置，以及用于在感测操作期间从存储器单元感测位线及其补码之间的电流差的装置。

公开(公告)号：US08189367B1

公开(公告)日：2012-05-29

申请号：US12028042

申请日：2008-02-08

Applicant: David C. Lawson ,  Jason F. Ross

Inventor： David C. Lawson ,  Jason F. Ross

IPC: G11C11/00

CPC classification number: G11C11/4125

Abstract: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.

Abstract translation: 公开了在静态随机存取存储器中使用的单个事件镦粗（SEU）硬化存储单元。 SEU硬化存储单元包括第一晶体管，第二晶体管和连接在第一晶体管的源极和第二晶体管的漏极之间的第一电阻器。 SEU硬化存储单元还包括连接在第三晶体管的源极和第四晶体管的漏极之间的第三晶体管，第四晶体管和第二电阻器。 第一电阻器也连接在第三晶体管的栅极和第二晶体管的漏极之间。 第二电阻器也连接在第一晶体管的栅极和第四晶体管的漏极之间。

公开(公告)号：US07468904B2

公开(公告)日：2008-12-23

申请号：US11678097

申请日：2007-02-23

Applicant: David C. Lawson ,  Jason Ross

Inventor： David C. Lawson ,  Jason Ross

IPC: G11C11/00

CPC classification number: G11C11/4125

Abstract: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a second resistor and a capacitor. The first resistor is connected between an input of the first inverter and an output of the second inverter. The second resistor is connected between an input of the second inverter and an output of the first inverter. The capacitor is connected between an input of the first inverter and an input of the second inverter.

Abstract translation: 公开了在静态随机存取存储器中使用的单个事件镦粗（SEU）硬化存储单元。 SEU硬化存储单元包括以交叉耦合方式彼此连接的第一反相器和第二反相器。 SEU硬化存储单元还包括第一电阻器，第二电阻器和电容器。 第一电阻器连接在第一反相器的输入端和第二反相器的输出端之间。 第二电阻器连接在第二反相器的输入端和第一反相器的输出端之间。 电容器连接在第一反相器的输入端和第二反相器的输入端之间。

公开(公告)号：US20120120704A1

公开(公告)日：2012-05-17

申请号：US12028042

申请日：2008-02-08

Applicant: David C. Lawson ,  Jason F. Ross

Inventor： David C. Lawson ,  Jason F. Ross

IPC: G11C5/06 ,  G11C11/00 ,  G11C11/40

CPC classification number: G11C11/4125

Abstract: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of a the second transistor. The second resistor is also connected between a gate of a the first transistor and the drain of the fourth transistor.

Abstract translation: 公开了在静态随机存取存储器中使用的单个事件镦粗（SEU）硬化存储单元。 SEU硬化存储单元包括第一晶体管，第二晶体管和连接在第一晶体管的源极和第二晶体管的漏极之间的第一电阻器。 SEU硬化存储单元还包括连接在第三晶体管的源极和第四晶体管的漏极之间的第三晶体管，第四晶体管和第二电阻器。 第一电阻器也连接在第三晶体管的栅极和第二晶体管的漏极之间。 第二电阻器还连接在第一晶体管的栅极和第四晶体管的漏极之间。

公开(公告)号：US20100079183A1

公开(公告)日：2010-04-01

申请号：US12286286

申请日：2008-09-30

Applicant: David C. Lawson ,  Michael A. Belzecky

Inventor： David C. Lawson ,  Michael A. Belzecky

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/356113 ,  H03K3/356182 ,  H03K19/00338 ,  H03K19/00392

Abstract: Tri-stating transistors which are controlled by the latch enable lines isolate holding transistors from the latch node during setting of the latch. The tri-stating transistors are connected to the holding transistors and the latch node which allows the node to float and assume a third state during setting of the latch when the latch is enabled.

Abstract translation: 由锁存器使能线控制的三态晶体管在锁存器的置位期间将保持晶体管与锁存器节点隔离。 三态晶体管连接到保持晶体管和锁存节点，当锁存器被使能时，锁存节点允许节点浮动并且在锁存器的设置期间呈现第三状态。