公开(公告)号：US20060220096A1

公开(公告)日：2006-10-05

申请号：US11133718

申请日：2005-05-19

Applicant: Bin Wang ,  Yanjun Ma

Inventor： Bin Wang ,  Yanjun Ma

IPC: H01L29/788

CPC classification number: G11C16/045 ,  G11C16/0416 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

Abstract: Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and a surface region on a substrate are implanted with the impurities based on a number of predetermined configurations. In another embodiment, a transistor type semiconductor device is configured with implanted impurities in two regions of its floating gate as well as two surface regions in its substrate. Enhanced tunneling junction enables use of lower tunneling voltages in applications such as programming NVM cells.

Abstract translation: 描述了隧道增强型浮栅半导体器件及其形成方法。 在一个实施例中，p-n结器件形成有部分掺杂有n型和p型杂质的浮栅。 基于多个预定配置，在浮置栅极中的n +掺杂区域的任一侧上的两个区域和衬底上的表面区域注入杂质。 在另一个实施例中，晶体管型半导体器件被配置为在其浮动栅极的两个区域中具有注入的杂质以及其衬底中的两个表面区域。 增强的隧道结使得能够在诸如编程NVM单元之类的应用中使用较低的隧道电压。

公开(公告)号：US08805669B2

公开(公告)日：2014-08-12

申请号：US13182281

申请日：2011-07-13

Applicant: Yifan He ,  Yanjun Ma ,  Andrew Way ,  Josef van Genabith

Inventor： Yifan He ,  Yanjun Ma ,  Andrew Way ,  Josef van Genabith

IPC: G06F17/28

CPC classification number: G06F17/2836

Abstract: A translation system for translating source text from a first language to target text in a second language. The system comprises a translation memory (TM) module that stores translation segments. The TM module is operable to generate a TM target text output in response to source text. A statistical translation machine (SMT) module is configured to generate translations on the basis of statistical models whose parameters are derived from the analysis of bilingual text corpora. The SMT module is operable to generate a SMT target text output in response to source text. An extractor is configured to extract features from the TM target text output and the SMT target text output. A vector generator is configured to generate a vector with a unified feature set derived from the extracted features and features associated with the SMT module and the TM module. A recommender is operable to read the vector and determine whether the TM target text output or the SMT target text output is optimum for post editing.

Abstract translation: 用于将源文本从第一语言翻译成以第二语言定向文本的翻译系统。 该系统包括存储翻译段的翻译记忆（TM）模块。 TM模块可操作以响应于源文本生成TM目标文本输出。 统计翻译机（SMT）模块被配置为基于其参数来自双语文本语料库的分析的统计模型生成翻译。 SMT模块可操作以响应于源文本生成SMT目标文本输出。 提取器被配置为从TM目标文本输出和SMT目标文本输出中提取特征。 向量生成器被配置为生成具有从提取的特征和与SMT模块和TM模块相关联的特征导出的统一特征集的向量。 推荐器可操作以读取该矢量并确定TM目标文本输出或SMT目标文本输出是否适于后期编辑。

公开(公告)号：US07808823B2

公开(公告)日：2010-10-05

申请号：US12020522

申请日：2008-01-26

Applicant: Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

Inventor： Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

IPC: G11C16/06

CPC classification number: G11C29/789 ,  G11C29/76

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.

Abstract translation: 两个浮置栅极器件以无线电频率识别（RFID）标签的非易失性存储器（NVM）中的冗余配置被布置，使得应力感应漏电流（SILC）或其他故障不会导致存储器存储器的完全丢失 。 冗余NVM可以被布置为串联配置，并行配置，单端设备，差分设备，简单逻辑电路功能和/或复杂逻辑电路功能。

公开(公告)号：US20080136602A1

公开(公告)日：2008-06-12

申请号：US12020522

申请日：2008-01-26

Applicant: Yanjun Ma ,  Willian T. Colleran ,  Vadim Gutnik

Inventor： Yanjun Ma ,  Willian T. Colleran ,  Vadim Gutnik

IPC: G11C16/06

CPC classification number: G11C29/789 ,  G11C29/76

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.

Abstract translation: 两个浮置栅极器件以无线电频率识别（RFID）标签的非易失性存储器（NVM）中的冗余配置被布置，使得应力感应漏电流（SILC）或其他故障不会导致存储器存储器的完全丢失 。 冗余NVM可以被布置为串联配置，并行配置，单端设备，差分设备，简单逻辑电路功能和/或复杂逻辑电路功能。

公开(公告)号：US06759695B2

公开(公告)日：2004-07-06

申请号：US10661429

申请日：2003-09-11

Applicant: Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

Inventor： Yanjun Ma ,  Douglas James Tweet ,  David Russell Evans

IPC: H01L29788

CPC classification number: H01L29/66916 ,  H01L29/802

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract translation: 集成电路金属氧化物半导体器件包括位于其中的栅极区域和电介质层，其中介电层基本上不含有从器件的硅锗层扩散的锗。 该方法包括沉积虚拟置换栅极，对器件进行高温处理，去除伪栅极，然后在所形成的栅极区域内沉积介电材料和最终栅极材料。 因为在器件的高温处理之后沉积介电材料，所以锗可以扩散到电介质材料中。

公开(公告)号：US06632731B2

公开(公告)日：2003-10-14

申请号：US09783760

申请日：2001-02-14

Applicant: Yanjun Ma ,  David Russell Evans ,  Yoshi Ono ,  Sheng Teng Hsu

Inventor： Yanjun Ma ,  David Russell Evans ,  Yoshi Ono ,  Sheng Teng Hsu

IPC: H01L213205

CPC classification number: H01L29/6659 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/82385 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract translation: 制造亚微米MOS晶体管的方法包括制备衬底，包括在其中分离有源区; 沉积栅氧化层; 在所述栅极氧化物层上沉积第一选择性可蚀刻层; 在第一选择性可蚀刻层上沉积第二选择性可蚀刻层; 蚀刻结构以切割第一选择性可蚀刻层; 在有源区中注入离子以形成源区和漏区; 沉积和平坦化氧化物; 去除剩余的第一选择性可蚀刻层和第二选择性可蚀刻层; 沉积栅电极; 并沉积氧化物并金属化该结构。 亚微米MOS晶体管包括基板; 和有源区，包括具有小于1微米长度的栅区; 源区域，包括LDD源区域; 以及包括LDD漏极区域的漏极区域

公开(公告)号：US06573134B2

公开(公告)日：2003-06-03

申请号：US09817834

申请日：2001-03-27

Applicant: Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

Inventor： Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC: H01L218238

CPC classification number: H01L21/823842 ,  H01L27/092

Abstract: A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

公开(公告)号：US06441417B1

公开(公告)日：2002-08-27

申请号：US09820022

申请日：2001-03-28

Applicant: Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Yanjun Ma ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC: H01L2972

CPC classification number: H01L21/28291 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/516

Abstract: A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.

Abstract translation: 薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。 在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

公开(公告)号：US08759937B2

公开(公告)日：2014-06-24

申请号：US11387515

申请日：2006-03-22

Applicant: Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

Inventor： Yanjun Ma ,  Ronald A. Oliver ,  Todd E. Humes ,  Jaideep Mavoori

IPC: H01L27/095 ,  H01L29/872 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66143

Abstract: A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

Abstract translation: 在传统的CMOS工艺中制造了具有改进的性能和多阱结构的肖特基结二极管器件。 形成包括掺杂到第一导电类型的材料的衬底。 第一阱设置在衬底上。 第一阱包括不同掺杂的材料，例如与第一导电类型相反的第二导电类型。 第二口井设置在第一井内。 含金属材料的区域设置在第二阱中以在含金属材料区域和第二阱之间的界面处形成肖特基结。 在一个实施例中，第二井接触设置在第二井的一部分中。

公开(公告)号：US07843032B1

公开(公告)日：2010-11-30

申请号：US11965307

申请日：2007-12-27

Applicant: Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

Inventor： Cong Khieu ,  Yanjun Ma ,  Jaideep Mavoori

IPC: H01L21/82

CPC classification number: H01L27/0251

Abstract: Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 装置，系统和方法可以包括通过使用具有非对准门的半导体电路来管理射频识别（RFID）装置中的静电放电事件来实现快速反向电压保护机制。 这样的电路可以通过掺杂半导体衬底以形成第一导电区域而形成，以形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域 与源极区域和漏极区域中的一个重叠，并且形成集成电路，该集成电路包括被衬底支撑以耦合到源区域和漏极区域中的一个的RFID电路，以在节点处提供快速恢复电压操作 在集成电路和源极或漏极区之间。 公开了附加装置，系统和方法。