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    STRAINED TRANSISTOR INTEGRATION FOR CMOS
    2.
    发明申请
    STRAINED TRANSISTOR INTEGRATION FOR CMOS 失效
    CMOS的应变晶体管集成

    公开(公告)号：US20130153965A1

    公开(公告)日：2013-06-20

    申请号：US13764675

    申请日：2013-02-11

    申请人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    发明人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

    摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

    摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

    Strained transistor integration for CMOS
    5.
    发明授权
    Strained transistor integration for CMOS 失效
    用于CMOS的应变晶体管集成

    公开(公告)号：US07662689B2

    公开(公告)日：2010-02-16

    申请号：US10747321

    申请日：2003-12-23

    申请人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    发明人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

    IPC分类号： H01L21/8236

    CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

    摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

    摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

    Non-planar MOS structure with a strained channel region
    8.
    发明授权
    Non-planar MOS structure with a strained channel region 有权
    具有应变通道区域的非平面MOS结构

    公开(公告)号：US07531393B2

    公开(公告)日：2009-05-12

    申请号：US11373776

    申请日：2006-03-09

    申请人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

    发明人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    摘要： An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

    摘要翻译： 一个实施例是包括应变通道区域的非平面MOS晶体管结构。 具有应变通道优点的非平面MOS晶体管结构，特别是NMOS三栅极晶体管的组合产生了对于给定栅极长度宽度相对于非晶体管的晶体管驱动电流，开关速度和降低的漏电流 具有包含应变通道的无约束通道或平面MOS结构的平面MOS结构。

    Tri-gate transistors and methods to fabricate same
    9.
    发明授权
    Tri-gate transistors and methods to fabricate same 有权
    三栅晶体管及其制造方法

    公开(公告)号：US07268058B2

    公开(公告)日：2007-09-11

    申请号：US10760028

    申请日：2004-01-16

    申请人： Robert Chau ,  Suman Datta ,  Brian S Doyle ,  Been-Yih Jin

    发明人： Robert Chau ,  Suman Datta ,  Brian S Doyle ,  Been-Yih Jin

    IPC分类号： H01L21/76

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

    摘要翻译： 本发明的实施例提供了一种用于对绝缘体上硅晶体管制造实现均匀的硅体高度的方法。 对于一个实施例，牺牲氧化物层设置在半导体衬底上。 氧化层被蚀刻以形成沟槽。 然后用半导体材料填充沟槽。 然后将半导体材料与氧化物层的其余部分平坦化，然后除去氧化物层的其余部分。 这样暴露的半导体鳍片具有均匀的高度，在规定的公差范围内。